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| 1 of 162 october 20, 2006 ? 2006 integrated device technology, inc. dsc 6214/- idt and the idt logo are trademarks of integrated device technology, inc. description the idt88k8483 is a 3-port spi-4 exchange device. the idt spi-4 exchange devices build on idt?s proven spi-4 implementation and packet fragment processor (pfp) design. the idt88k8483 suits appli- cations with slow backpress ure response and other advanced networking applications when there is the need for duplicate ports to re- route data multiple times through the packet-exchange and temporary storage for complete in-flight packets. the data on each spi-4 interface logical port (lp) are mapped to a logical identifier (lid). a data flow between logical port addresses on the various interfaces is accomplished using lid maps that can be dynami- cally reconfigured. the device enabl es the connection of two spi-4 devices to a network processor having one or more spi-4 interfaces. up to 18mbit of additional buffer memory can be provided using the qdrii interface. alternatively, the hstl i/o may be used to provide a generic packet interface to a fpga. the device supports a maximum of 128 logical ports. applications ? ethernet transport ? sonet / sdh packet transport line cards ? broadband aggregation ? multi-service switches ? ip services equipment ? security firewalls features functionality ? multiplexes logical ports (lps ) from spi-4a and spi-4b to spi- 4m ? optionally converts between interleaved packet transfers and whole packet transfers per logical port ? data redirection per lp between spi-4a, spi-4b and 10g fpga ? per lp configurable memory allocation ? per lp memory expansion via qdr-ii sram interface ? 3 separate clock generators allowing fully flexible, fully inte- grated clock derivations and generation standard interfaces ? two oif spi-4 phase 2: 80 - 450 mhz, 256 address range, 64 concurrently active lps per interface ? one oif spi-4 phase 2: 80 - 450 mhz, 256 address range, 128 concurrently active lps ? spi-4 fifo status channel options: ? lvds full-rate, lvds quarter-rate, lvttl quarter-rate ? spi-4 compatible with network processor streaming interface (npsi npe-framer mode of operation) ? hstl interface with selectable operating mode 160 - 200 mhz ddr packet interfac e, 64 concurrently active lps; or qdr-ii memory interface: 160 - 200mhz hstl ? serial or parallel microprocessor interface for control and monitoring ? ieee 1491.1 jtag block diagram figure 1 idt88k8483 block diagram spi-4a 64 logical qdr-ii 10gbps packet fragment processor a-tm (pfp) memory int. 10gbps fpga packet int. ports spi-4b 64 logical ports packet fragment processor a-mt (pfp) packet fragment processor b-tm (pfp) packet fragment processor b-mt (pfp) spi-4m 128 logical ports auxiliary 10gbps interface tributary spi-4s main spi-4 serial / 8bit microprocessor interface micro. int. jtag interface jtag int. idt88k8483 spi-4 exchange document issue 1.0
2 of 162 october 20, 2006 idt idt88k8483 table of contents description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 pin description table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 external interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 spi-4 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 insert and extract paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 packet fragment processor (pfp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 qdr-ii interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 generic interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 embedded processor download . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 pmon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 design consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 configuration sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 direct registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 indirect registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 miscellaneous registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 electrical and thermal specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 3 of 162 october 20, 2006 idt idt88k8483 list of figures figure 1. idt88k8483 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2. general data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 3. pfp structure example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 4. pfp allocation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 5. qdr-ii sram structure example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 6. qdr-ii allocation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 7. spi-4 ingress port buffer structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 8. spi-4 egress calendar example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 9. spi-4 tributary to spi-4 main data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 10. spi-4 main to spi-4 tributary data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 11. pfp loop data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 12. microprocessor, auxiliar y and internal traffic detector/generator data path . . . . . . . 38 figure 13. pfp redirect data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 14. idt88k8483 spi-4 connections example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 15. spi-4 ingress block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 16. spi-4 ingress state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 17. spi-4 egress state block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 18. egress word transition state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 19. status channel state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 20. pfp block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 21. pfp ingress flow control example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 22. pfp flow control example fo r over booking mode . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 23. idt88k8483 and idt7172604 qdr-ii sram connections . . . . . . . . . . . . . . . . . . . . . 55 figure 24. flow control mode 1 application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 25. qdr-ii fifos allocation example for buffering op tion . . . . . . . . . . . . . . . . . . . . . . . 57 figure 26. qdr-ii flow contro l example for buffering option . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 27. flow control mode 2 application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 28. idt88k8483 and fpga connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 29. generic interface - transfer format for normal data . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 30. generic interface - transfer format for stratus word. . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 31. microprocessor interface - parallel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 32. interrupt scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 33. pmon measure points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 figure 34. internal pmon time base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 35. external pmon time base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 36. clock generator type m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 37. clock generator type t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 figure 38. power-on-reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 39. jtag daisy chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 40. trstb signal during power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 41. idt88k8483 power supply generation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 42. idt88k8483 vdda25 filter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 43. idt88k8483 spi4x_vref filter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 44. indirect register access scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 45. indirect access module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 figure 46. auxiliary interface - qdr-ii / generic - write ac cess . . . . . . . . . . . . . . . . . . . . . . . . . 154 figure 47. auxiliary interface - qdr-ii / generic - read ac cess . . . . . . . . . . . . . . . . . . . . . . . . 154 figure 48. mcu interface - motorola mode - read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 figure 49. mcu interface - motorola mode - write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 figure 50. mcu interface - intel mode - read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 figure 51. mcu interface - intel mode - write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 figure 52. 88k8483 top view pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 figure 53. serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 4 of 162 october 20, 2006 idt idt88k8483 figure 54. jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 figure 55. br 672 fcbg package outline, rohs compliant . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 5 of 162 october 20, 2006 idt idt88k8483 list of tables table 1. idt88k8483 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 3. spi-4 status information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 table 4. generic interface - control field coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 table 5. field associated n on-critical event list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 table 6. field associated critical event list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 table 7. non field associated event list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 table 8. time base source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 table 9. clk_sel signals configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 table 10. div4 signal configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 table 11. jtag instruction code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 table 12. jtag id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 table 13. direct register table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 table 14. indirect register table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 table 15. direct registers map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 table 16. indirect registers map - segment base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 table 17. indirect registers map - module base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 table 18. indirect registers map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 table 19. global software reset register (regi ster offset=0x22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 table 20. microprocessor mailbox input fifo data register (register offset=0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 table 21. microprocessor mailbox i nput fifo length register (register offset=0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 table 22. microprocessor mailbox input fifo status register (regist er offset=0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 table 23. microprocessor mailbox out put fifo data register (register offset=0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 table 24. microprocessor mailbox ou tput fifo length register (register offset=0x13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 table 25. microprocessor mailbox input fifo status register (regist er offset=0x15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 table 26. embedded processor state regi ster (register offset=0x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 table 27. microprocessor indirect a ccess control register (register offset=0x1a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 table 28. microprocessor indirect access error codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 table 29. microprocessor indirect access data register -1 (register offset=0x1b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 table 30. microprocessor indirect access data register - 2 (register offset=0x1c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 table 31. microprocessor indirect access data register - 3 (register offset=0x1d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 table 32. microprocessor indirect access data register - 4 (register offset=0x1e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 table 33. microprocessor indirect a ccess address register - 1 (register offset=0x1f) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 table 34. microprocessor indirect a ccess address register - 2 (register offset=0x20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 table 35. microprocessor indirect a ccess address register - 3 (register offset=0x21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 table 36. pfp t-m insert control register (r egister offset=0x0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 table 37. pfp t-m insert data register(register offset=0x1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 table 38. pfp t-m extract control register (r egister offset=0x2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 table 39. pfp t-m extract data register (regist er offset=0x3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 table 40. pfp m-t insert control register (r egister offset=0x4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 table 41. pfp m-t insert data register (register offset=0x5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 table 42. pfp m-t extract control register (r egister offset=0x6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 table 43. pfp m-t extract data register (regist er offset=0x7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 table 44. primary interrupt indication register (register offset=0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 table 45. primary interrupt enable register (register offset=0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 table 46. secondary module indication register (register offset=0x0a.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 table 47. secondary module enable register (regi ster offset=0x0b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 table 48. secondary interrupt module b indicati on register(register offset=0xc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 table 49. secondary interrupt module b enable regi ster (register offset=0xd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 table 50. interrupt secondary common indicati on register (register offset=0xe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 table 51. interrupt secondary common enable r egister (register_offset=0xf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 table 52. mclk divider sticky register (blo ck base=0x0a00, register offset=0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 table 53. clock control input status register (block base=0x0a00, register offset=0x01) . . . . . . . . . . . . . . . . . . . . . . . . . .104 6 of 162 october 20, 2006 idt idt88k8483 table 54. spi-4 ingress lp to lid mapping table (block base=0x0000, register offset=0x00-0xff) . . . . . . . . . . . . . . . . . . .105 table 55. spi-4 ingress calendar 0 table (blo ck base=0x0100, register offset=0x00-0x3f/0x7f) . . . . . . . . . . . . . . . . . . . . .105 table 56. ingress calendar 1 table (block base =0x0200, register offset=0x 00-0x3f/0x7f) . . . . . . . . . . . . . . . . . . . . . . . . . .105 table 57. spi-4 interface enable register (blo ck base= 0x0300, register offset=0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 table 58. spi-4 ingress configurat ion register (block base=0x0300, register offset=0x01) . . . . . . . . . . . . . . . . . . . . . . . .106 table 59. spi-4 ingress training pa rameter register (block base=0x0300, register o ffset=0x02) . . . . . . . . . . . . . . . . . . . .107 table 60. spi-4 ingress calendar 0 configurat ion register (block base=0x0300, register o ffset=0x03) . . . . . . . . . . . . . . .107 table 61. spi-4 ingress calendar 1 configurat ion register (block base=0x0300, register offset=0x04) . . . . . . . . . . . . . . .108 table 62. spi-4 ingress status register (blo ck base=0x0300, register offset=0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 table 63. spi-4 ingress diagnostics register (block base=0x0300, register offset=0x06) . . . . . . . . . . . . . . . . . . . . . . . . . .109 table 64. spi-4 ingress automatic alignment c ontrol register (block base=0x0300, register offset=0x07) . . . . . . . . . . . . . 109 table 65. spi-4 ingress calendar switch control register (block base=0x0300, register offset=0x08) . . . . . . . . . . . . . . . .109 table 66. ingress calendar switch register: bit cal_sel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 table 67. ingress calendar switch register: bit i_dip_csw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 table 68. spi-4 ingress fill level register (block base=0x0300, r egister offset=0x0b-0x0c) . . . . . . . . . . . . . . . . . . . . . . . .110 table 69. spi-4 ingress max fill lev el register (block base=0x0300, register offs et=0x0d-0x0e . . . . . . . . . . . . . . . . . . . .110 table 70. spi-4 ingress watermark register (block base=0x0300, register offset=0 x0f-0x10) . . . . . . . . . . . . . . . . . . . . . .111 table 71. ingress training to out of sync threshold registe(block base=0x0300,register offset=0x13) . . . . . . . . . . . . . . . .111 table 72. spi-4 egress lid to lp mapping table (block base=0x0400, register offset=0x00-0x3f/0x7f) . . . . . . . . . . . . .111 table 73. spi-4 egress calendar 0 table (block base=0x0500, register offset=0x00-0x3f/0x7f) . . . . . . . . . . . . . . . . . . . .111 table 74. spi-4 egress calendar 1 table (block base=0x0600, register offset=0x00-0x3f/0x7f) . . . . . . . . . . . . . . . . . . . .112 table 75. spi-4 egress configuration register (block base=0x0800, register offset=0x01) . . . . . . . . . . . . . . . . . . . . . . . . .113 table 76. spi-4 egress training parameter register (block base=0x 0800, register offset=0x02) . . . . . . . . . . . . . . . . . . . .113 table 77. spi-4 egress calendar 0 configuratio n register (block base=0x0800, register offset=0x03) . . . . . . . . . . . . . . . .114 table 78. spi-4 egress calendar 1 configuratio n register (block base=0x0800, register offset=0x04) . . . . . . . . . . . . . . . .114 table 79. spi-4 egress status register (block base=0x0800, register offset=0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 table 80. spi-4 egress diagnostics r egister (block base=0x0800, register offset=0x06) . . . . . . . . . . . . . . . . . . . . . . . . . .115 table 81. spi-4 egress automatic alignment c ontrol register (block base=0x0800, register offset=0x07) . . . . . . . . . . . . .1 15 table 82. spi-4 egress calendar switch contro l register (block base = 0x0800, register offset=0x08) . . . . . . . . . . . . . . .116 table 83. spi-4 egress fill level register (block base=0x0800, regi ster offset = 0x0b and 0x0c) . . . . . . . . . . . . . . . . . . .116 table 84. spi-4 egress max fill level register (block base =0x0800, register offset = 0x0d and 0x0e) . . . . . . . . . . . . . .116 table 85. spi-4 histogram measure launch regist er (block base=0x0900 register offset=0x00) . . . . . . . . . . . . . . . . . . . .117 table 86. spi-4 histogram measure status register (block base=0x 0900 register offset=0x01) . . . . . . . . . . . . . . . . . . . . .117 table 87. spi-4 histogram counter register (b lock base=0x0900 register offset=0x02-0x0b) . . . . . . . . . . . . . . . . . . . . . .117 table 88. spi-4 bit alignment result register (block base=0x0900 register offset=0x0c-0x1e) . . . . . . . . . . . . . . . . . . . . .118 table 89. spi-4 egress data lane timing control (block base=0x0900, register offset=0x2a) . . . . . . . . . . . . . . . . . . . . . .118 table 90. spi-4 egress data control lane timing control (block ba se=0x0900, register offset=0x2b) . . . . . . . . . . . . . . . .118 table 91. spi-4 egress data clock timing c ontrol (blockbase=0x0900, register offset=0x2c) . . . . . . . . . . . . . . . . . . . . . .119 table 92. spi-4 egress status timing control (block base=0x0900, r egister offset=0x2d) . . . . . . . . . . . . . . . . . . . . . . . . .119 table 93. spi-4 egress status clock timing control (block base=0x0900, register offset=0x2e) . . . . . . . . . . . . . . . . . . . .120 table 94. pfp buffer segment assign table (block base=0x01000/0x1800, register offset=0x00-0x3f) . . . . . . . . . . . . . .120 table 95. pfp packet length thresholds (block base=0x1100/0x1900, regi ster offset=0x00-03f) . . . . . . . . . . . . . . . . . . .121 table 96. pfp queue diagnose table (block base=0 x1200/0x1a00, register offset=0x00-0x3f) . . . . . . . . . . . . . . . . . . . .121 table 97. pfp packet diagnose table (block base =0x1300/0x1b00, register offset=0x00-03f) . . . . . . . . . . . . . . . . . . . . .121 table 98. pfp egress burst size table (block base=0x1400/0x1c00, register offset=0x00-0x3f) . . . . . . . . . . . . . . . . . . .122 table 99. pfp egress weight and direction register (block base=0x1500/0x1d00, regist er offset=0x00-03f) . . . . . . . . .122 table 100. pfp egress packet mode control register (block base=0 x1600/0x1e00, register offset=0 x00-0x3f) . . . . . . . . .123 table 101. pfp link number confi guration register (block base=0x1700/0x1f00, regist er offset=0x00) . . . . . . . . . . . . . . . 123 table 102. pfp buffer management configuration re gister (block base=0x1700/0x1f00, regist er offset=0x01) . . . . . . . . .123 table 103. pfp queue weighting enable register (block base=0x1700/0x1f00, register o ffset=0x02) . . . . . . . . . . . . . . . . 124 table 104. pfp flow control register (block base=0x1700/0x1f00, regi ster offset=0x03) . . . . . . . . . . . . . . . . . . . . . . . . . .125 table 105. pfp test register (block base=0x 1700/0x1f00, register offset=0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 table 106. pfp ingress status monitor register - 1 (block base=0x1700/0x1f00, register offset=0x05) . . . . . . . . . . . . . . . .126 table 107. pfp ingress status monitor register - 2 (block base=0x1700/0x1f00, register offset=0x06) . . . . . . . . . . . . . . . .126 7 of 162 october 20, 2006 idt idt88k8483 table 108. pfp ingress status monitor register - 3 (block base=0x1700/0x1f00, register offset=0x07) . . . . . . . . . . . . . . . .126 table 109. pfp ingress status monitor register - 4 (block base=0x1700/0x1f00, register offset=0x08) . . . . . . . . . . . . . . . .126 table 110. pfp egress status monitor register - 1 (block base=0x1700/0x1f00, register offset=0x09) . . . . . . . . . . . . . . . .127 table 111. pfp egress status monitor register - 2 (block base=0x1700/0x1f00, register offset=0x0a) . . . . . . . . . . . . . . . .127 table 112. pfp egress status monitor register - 3 (block base=0x1700/0x1f00, register offset=0x0b) . . . . . . . . . . . . . . . .127 table 113. pfp egress status monitor register - 4 (block base=0x1700/0x1f00, register offset=0x0c) . . . . . . . . . . . . . . . .127 table 114. pfp internal parity error indicati on register (block base=0x1700/0x1f00, regist er offset=0x0d) . . . . . . . . . . . .127 table 115. pfp maximum packet length register (block base=0x1700/0x1f 00, register offset=0x0e) . . . . . . . . . . . . . . . .1 28 table 116. auxiliary interface enable register (block base=0x0a00, register offset=0x00) . . . . . . . . . . . . . . . . . . . . . . . . . .129 table 117. auxiliary interface configuration register (block base=0 x0a00, register offset=0x01) . . . . . . . . . . . . . . . . . . . . .129 table 118. auxiliary extension buffer configurat ion register (block base=0x0a00, register offset=0x02) . . . . . . . . . . . . . . .129 table 120. auxiliary clock monitor status regi ster (block base=0x0a00, register offset=0x03) . . . . . . . . . . . . . . . . . . . . . . .130 table 121. external memory test control register (block base=0x0a 00, register offset=0x04) . . . . . . . . . . . . . . . . . . . . . . .130 table 119. external memory segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 table 122. external memory test results regist er (block base=0x0a00, register offset=0x05) . . . . . . . . . . . . . . . . . . . . . .131 table 123. auxiliary early backpressure threshold register (block base=0x0a00, register offset=0x07) . . . . . . . . . . . . . . .131 table 124. auxiliary packet mode configuration register (block base =0x0a00, register offset=0x08) . . . . . . . . . . . . . . . . .131 table 125. auxiliary hstl receiver test control register (block ba se=0x0a00, register offset=0x0e) . . . . . . . . . . . . . . . .131 table 126. auxiliary automatic impedance matching control register (block base=0x0a00, r egister offset=0x0f) . . . . . . . .132 table 127. auxiliary synchronization status register (block base=0x0 a00, register offset=0x12) . . . . . . . . . . . . . . . . . . . . .132 table 128. auxiliary initialization control register (block base=0x0 a00, register offset=0x013) . . . . . . . . . . . . . . . . . . . . . .133 table 129. enable control register (block base=0x0b00, register o ffset=0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 table 130. feedback configuration register (block base=0x0b00, regi ster offset=0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . .133 table 131. bandwidth control register (block base=0x0b00, register offset=0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 table 132. bandwidth level as per field bw. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 table 133. packet length register (block base=0 x0b00, register offset=0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 table 134. burst size register (block base=0 x0b00, register offset=0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 table 135. random control register (block base =0x0b00, register offset=0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 table 136. lid register (block base=0x0b00, register offset=0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 table 137. synchronization register (block base =0x0b00, register offset=0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 table 138. bit error insertion register (block base=0x0b00, regist er offset=0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 table 139. pmon event interrupt indication regi ster (block base=0x0f00, register offset=0x00) . . . . . . . . . . . . . . . . . . . . .136 table 140. pmon event interrupt enable register (block base=0x0f00, register offset=0x01) . . . . . . . . . . . . . . . . . . . . . . .139 table 141. pmon buffer t-m overflow indication register (block base=0x0f00, register o ffset=0x02-0x03) . . . . . . . . . . . .14 0 table 142. pmon buffer m-t overflow indication register (block base=0x0f00, regist er offset=0x04-0x05) . . . . . . . . . . . .14 1 table 143. pmon buffer t-m overflow interrupt control register (block base=0x0f00, r egister offset=0x06-0x07) . . . . . . .141 table 144. pmon buffer m-t overflow interrupt control register (block base=0x0f 00, register offset=0x08-0x09) . . . . . . .141 table 145. pmon buffer overflow source regist er (block base=0x0f00, register offset=0 x0a) . . . . . . . . . . . . . . . . . . . . . .142 table 146. pmon t-m inactive transfer lp field register (block base=0x0f00, register offset=0x0b) . . . . . . . . . . . . . . . .142 table 147. pmon m-t inactive transfe r lp field register (block base=0x0f00, regist er offset=0x0c) . . . . . . . . . . . . . . . .142 table 148. pmon t-m illegal sop event field r egister (block base=0x0f00, register offset=0x0d) . . . . . . . . . . . . . . . . . .142 table 149. pmon t-m illegal eop event field r egister (block base=0x0f00, register offset=0x0e) . . . . . . . . . . . . . . . . . .142 table 150. pmon m-t illegal sop event field register (block base=0x0f00, register offset=0x0f) . . . . . . . . . . . . . . . . . .143 table 151. pmon m-t illegal eop event field register (block base=0x0f00, register offset=0x10) . . . . . . . . . . . . . . . . . .143 table 152. pmon t-m packet cut-down lid field register (block base =0x0f00, register offset=0x11) . . . . . . . . . . . . . . .1 43 table 153. pmon m-t packet cut-down lid field register (block base=0x0f00, register offset=0x12) . . . . . . . . . . . . . . .1 43 table 154. pmon per lid counter table (block base=0x0c00, register offset=0x00-0x17f) . . . . . . . . . . . . . . . . . . . . . . . .144 table 155. pmon per module/interface counter table (block base=0x0 e00 register offset=0x00-0x10 . . . . . . . . . . . . . . . .1 44 table 156. pmon timebase control register (blo ck base=0x8b00, register offset=0x00) . . . . . . . . . . . . . . . . . . . . . . . . . .145 table 157. timebase source table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 table 158. pmon 1ms timer register (block base=0x8b00, register offset=0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 table 159. gpio direction register (block ba se=0x8b00, register offset=0x10-0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 table 160. gpio level register (block base=0x8 b00, register offset=0x13-0x15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 table 161. gpio link table (block base=0x8b00, register offset=0x16-0x18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 8 of 162 october 20, 2006 idt idt88k8483 table 162. version number register (block base=0x8b00, register offset=0x30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 table 163. version number register (block base=0x8b00, register offset=0x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 table 164. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 table 165. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 table 166. thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 table 167. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 table 168. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 table 169. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 table 170. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161 9 of 162 october 20, 2006 idt idt88k8483 pin assignment the following table shows the idt88k 8483 pins and their corresponding symbols. function pin adr0 e1 adr1 e2 adr2 d2 adr3 c4 adr4 d3 adr5 b4 bond0 r6 bond1 p6 csb d5 dat0 a5 dat1 a4 dat2 a3 dat3 b3 dat4 c3 dat5 c2 dat6 c1 dat7 d1 div4 ab6 gpio0 ae5 gpio1 ad5 gpio2 ac5 intb d4 mpm e4 qdr_a0 l24 qdr_a1 m24 qdr_a10 r24 qdr_a11 r23 qdr_a12 r22 qdr_a13 t21 qdr_a14 r21 qdr_a15 p21 qdr_a16 n21 qdr_a17 m21 qdr_a2 n24 table 1 idt88k8483 pinout (part 1 of 19) 10 of 162 october 20, 2006 idt idt88k8483 qdr_a3 n23 qdr_a4 n22 qdr_a5 p22 qdr_a6 p23 qdr_a7 p24 qdr_a8 p25 qdr_a9 p26 qdr_cq n26 qdr_cqb n25 qdr_d0 d25 qdr_d1 h22 qdr_d10 k23 qdr_d11 k24 qdr_d12 k25 qdr_d13 m22 qdr_d14 m23 qdr_d15 k26 qdr_d16 h26 qdr_d17 f26 qdr_d18 r25 qdr_d19 u26 qdr_d2 f23 qdr_d20 w26 qdr_d21 u25 qdr_d22 w25 qdr_d23 u24 qdr_d24 w24 qdr_d25 u23 qdr_d26 u22 qdr_d27 ac26 qdr_d28 aa26 qdr_d29 ac25 qdr_d3 h23 qdr_d30 y25 qdr_d31 y24 qdr_d32 aa23 qdr_d33 aa22 function pin table 1 idt88k8483 pinout (part 2 of 19) 11 of 162 october 20, 2006 idt idt88k8483 qdr_d34 w23 qdr_d35 w22 qdr_d4 f24 qdr_d5 h24 qdr_d6 f25 qdr_d7 h25 qdr_d8 d26 qdr_d9 k22 qdr_imp ad25 qdr_k l26 qdr_kb l25 qdr_q0 c25 qdr_q1 g22 qdr_q10 j23 qdr_q11 j24 qdr_q12 j25 qdr_q13 l22 qdr_q14 l23 qdr_q15 j26 qdr_q16 g26 qdr_q17 e26 qdr_q18 r26 qdr_q19 t26 qdr_q2 f22 qdr_q20 v26 qdr_q21 t25 qdr_q22 v25 qdr_q23 t24 qdr_q24 v24 qdr_q25 t23 qdr_q26 t22 qdr_q27 ab26 qdr_q28 y26 qdr_q29 ab25 qdr_q3 g23 qdr_q30 aa25 qdr_q31 aa24 function pin table 1 idt88k8483 pinout (part 3 of 19) 12 of 162 october 20, 2006 idt idt88k8483 qdr_q32 y23 qdr_q33 y22 qdr_q34 v23 qdr_q35 v22 qdr_q4 e24 qdr_q5 g24 qdr_q6 e25 qdr_q7 g25 qdr_q8 c26 qdr_q9 j22 qdr_rb k21 qdr_vref ad26 qdr_wb l21 rdb c5 resetb af4 spi4a_bias a24 spi4a_clk_sel f21 spi4a_ectl_n d15 spi4a_ectl_p d14 spi4a_ed[0]_n e15 spi4a_ed[0]_p e14 spi4a_ed[1]_n e17 spi4a_ed[1]_p e16 spi4a_ed[10]_n a19 spi4a_ed[10_p a18 spi4a_ed[11]_n e21 spi4a_ed[11]_p e20 spi4a_ed[12]_n d21 spi4a_ed[12]_p d20 spi4a_ed[13]_n d22 spi4a_ed[13]_p e22 spi4a_ed[14]_n c21 spi4a_ed[14]_p c20 spi4a_ed[15]_n b21 spi4a_ed[15]_p b20 spi4a_ed[2]_n d17 spi4a_ed[2]_p d16 function pin table 1 idt88k8483 pinout (part 4 of 19) 13 of 162 october 20, 2006 idt idt88k8483 spi4a_ed[3]_n c17 spi4a_ed[3]_p c16 spi4a_ed[4]_n b17 spi4a_ed[4]_p b16 spi4a_ed[5]_n a17 spi4a_ed[5]_p a16 spi4a_ed[6]_n e19 spi4a_ed[6]_p e18 spi4a_ed[7]_n d19 spi4a_ed[7]_p d18 spi4a_ed[8]_n c19 spi4a_ed[8]_p c18 spi4a_ed[9]_n b19 spi4a_ed[9]_p b18 spi4a_edclk_n a21 spi4a_edclk_p a20 spi4a_esclk_n a7 spi4a_esclk_p a6 spi4a_esclk_t d6 spi4a_esta[0]_n c7 spi4a_esta[0]_p c6 spi4a_esta[1]_n b7 spi4a_esta[1]_p b6 spi4a_esta_t0 e7 spi4a_esta_t1 d7 spi4a_ictl_n e9 spi4a_ictl_p e8 spi4a_id[0]_n d9 spi4a_id[0]_p d8 spi4a_id[1]_n c9 spi4a_id[1]_p c8 spi4a_id[10]_n d13 spi4a_id[10]_p d12 spi4a_id[11]_n c13 spi4a_id[11]_p c12 spi4a_id[12]_n b13 spi4a_id[12]_p b12 function pin table 1 idt88k8483 pinout (part 5 of 19) 14 of 162 october 20, 2006 idt idt88k8483 spi4a_id[13]_n a13 spi4a_id[13]_p a12 spi4a_id[14]_n c15 spi4a_id[14]_p c14 spi4a_id[15]_n b15 spi4a_id[15]_p b14 spi4a_id[2]_n b9 spi4a_id[2]_p b8 spi4a_id[3]_n a9 spi4a_id[3]_p a8 spi4a_id[4]_n e11 spi4a_id[4]_p e10 spi4a_id[5]_n d11 spi4a_id[5]_p d10 spi4a_id[6]_n c11 spi4a_id[6]_p c10 spi4a_id[7]_n b11 spi4a_id[7]_p b10 spi4a_id[8]_n a11 spi4a_id[8]_p a10 spi4a_id[9]_n e13 spi4a_id[9]_p e12 spi4a_idclk_n a15 spi4a_idclk_p a14 spi4a_isclk_n a23 spi4a_isclk_p a22 spi4a_isclk_t c24 spi4a_ista[0]_n c23 spi4a_ista[0]_p c22 spi4a_ista[1]_n b23 spi4a_ista[1]_p b22 spi4a_ista_t0 d23 spi4a_ista_t1 d24 spi4a_lvdssta g21 spi4a_rclk e23 spi4a_vref b24 spi4b_bias af24 function pin table 1 idt88k8483 pinout (part 6 of 19) 15 of 162 october 20, 2006 idt idt88k8483 spi4b_clk_sel aa21 spi4b_ectl_n ac15 spi4b_ectl_p ac14 spi4b_ed[0]_n ab15 spi4b_ed[0]_p ab14 spi4b_ed[1]_n ab17 spi4b_ed[1]_p ab16 spi4b_ed[10]_n af19 spi4b_ed[10_p af18 spi4b_ed[11]_n ab21 spi4b_ed[11]_p ab20 spi4b_ed[12]_n ac21 spi4b_ed[12]_p ac20 spi4b_ed[13]_n ac22 spi4b_ed[13]_p ab22 spi4b_ed[14]_n ad21 spi4b_ed[14]_p ad20 spi4b_ed[15]_n ae21 spi4b_ed[15]_p ae20 spi4b_ed[2]_n ac17 spi4b_ed[2]_p ac16 spi4b_ed[3]_n ad17 spi4b_ed[3]_p ad16 spi4b_ed[4]_n ae17 spi4b_ed[4]_p ae16 spi4b_ed[5]_n af17 spi4b_ed[5]_p af16 spi4b_ed[6]_n ab19 spi4b_ed[6]_p ab18 spi4b_ed[7]_n ac19 spi4b_ed[7]_p ac18 spi4b_ed[8]_n ad19 spi4b_ed[8]_p ad18 spi4b_ed[9]_n ae19 spi4b_ed[9]_p ae18 spi4b_edclk_n af21 spi4b_edclk_p af20 function pin table 1 idt88k8483 pinout (part 7 of 19) 16 of 162 october 20, 2006 idt idt88k8483 spi4b_esclk_n af7 spi4b_esclk_p af6 spi4b_esclk_t ac6 spi4b_esta[0]_n ad7 spi4b_esta[0]_p ad6 spi4b_esta[1]_n ae7 spi4b_esta[1]_p ae6 spi4b_esta_t0 ab7 spi4b_esta_t1 ac7 spi4b_ictl_n ab9 spi4b_ictl_p ab8 spi4b_id[0]_n ac9 spi4b_id[0]_p ac8 spi4b_id[1]_n ad9 spi4b_id[1]_p ad8 spi4b_id[10]_n ac13 spi4b_id[10]_p ac12 spi4b_id[11]_n ad13 spi4b_id[11]_p ad12 spi4b_id[12]_n ae13 spi4b_id[12]_p ae12 spi4b_id[13]_n af13 spi4b_id[13]_p af12 spi4b_id[14]_n ad15 spi4b_id[14]_p ad14 spi4b_id[15]_n ae15 spi4b_id[15]_p ae14 spi4b_id[2]_n ae9 spi4b_id[2]_p ae8 spi4b_id[3]_n af9 spi4b_id[3]_p af8 spi4b_id[4]_n ab11 spi4b_id[4]_p ab10 spi4b_id[5]_n ac11 spi4b_id[5]_p ac10 spi4b_id[6]_n ad11 spi4b_id[6]_p ad10 function pin table 1 idt88k8483 pinout (part 8 of 19) 17 of 162 october 20, 2006 idt idt88k8483 spi4b_id[7]_n ae11 spi4b_id[7]_p ae10 spi4b_id[8]_n af11 spi4b_id[8]_p af10 spi4b_id[9]_n ab13 spi4b_id[9]_p ab12 spi4b_idclk_n af15 spi4b_idclk_p af14 spi4b_isclk_n af23 spi4b_isclk_p af22 spi4b_isclk_t ad24 spi4b_ista[0]_n ad23 spi4b_ista[0]_p ad22 spi4b_ista[1]_n ae23 spi4b_ista[1]_p ae22 spi4b_ista_t0 ac23 spi4b_ista_t1 ac24 spi4b_lvdsta y21 spi4b_rclk ab23 spi4b_vref ae24 spi4m_bias ad1 spi4m_clk_sel ae3 spi4m_ectl_n r4 spi4m_ectl_p p4 spi4m_ed[0]_n r5 spi4m_ed[0]_p p5 spi4m_ed[1]_n u5 spi4m_ed[1]_p t5 spi4m_ed[10]_n w1 spi4m_ed[10_p v1 spi4m_ed[11]_n aa5 spi4m_ed[11]_p y5 spi4m_ed[12]_n aa4 spi4m_ed[12]_p y4 spi4m_ed[13]_n ab4 spi4m_ed[13]_p ab5 spi4m_ed[14]_n aa3 function pin table 1 idt88k8483 pinout (part 9 of 19) 18 of 162 october 20, 2006 idt idt88k8483 spi4m_ed[14]_p y3 spi4m_ed[15]_n aa2 spi4m_ed[15]_p y2 spi4m_ed[2]_n u4 spi4m_ed[2]_p t4 spi4m_ed[3]_n u3 spi4m_ed[3]_p t3 spi4m_ed[4]_n u2 spi4m_ed[4]_p t2 spi4m_ed[5]_n u1 spi4m_ed[5]_p t1 spi4m_ed[6]_n w5 spi4m_ed[6]_p v5 spi4m_ed[7]_n w4 spi4m_ed[7]_p v4 spi4m_ed[8]_n w3 spi4m_ed[8]_p v3 spi4m_ed[9]_n w2 spi4m_ed[9]_p v2 spi4m_edclk_n aa1 spi4m_edclk_p y1 spi4m_esclk_n g1 spi4m_esclk_p f1 spi4m_esclk_t f4 spi4m_esta[0]_n g3 spi4m_esta[0]_p f3 spi4m_esta[1]_n g2 spi4m_esta[1]_p f2 spi4m_esta_t0 g5 spi4m_esta_t1 g4 spi4m_ictl_n j5 spi4m_ictl_p h5 spi4m_id[0]_n j4 spi4m_id[0]_p h4 spi4m_id[1]_n j3 spi4m_id[1]_p h3 spi4m_id[10]_n n4 function pin table 1 idt88k8483 pinout (part 10 of 19) 19 of 162 october 20, 2006 idt idt88k8483 spi4m_id[10]_p m4 spi4m_id[11]_n n3 spi4m_id[11]_p m3 spi4m_id[12]_n n2 spi4m_id[12]_p m2 spi4m_id[13]_n n1 spi4m_id[13]_p m1 spi4m_id[14]_n r3 spi4m_id[14]_p p3 spi4m_id[15]_n r2 spi4m_id[15]_p p2 spi4m_id[2]_n j2 spi4m_id[2]_p h2 spi4m_id[3]_n j1 spi4m_id[3]_p h1 spi4m_id[4]_n l5 spi4m_id[4]_p k5 spi4m_id[5]_n l4 spi4m_id[5]_p k4 spi4m_id[6]_n l3 spi4m_id[6]_p k3 spi4m_id[7]_n l2 spi4m_id[7]_p k2 spi4m_id[8]_n l1 spi4m_id[8]_p k1 spi4m_id[9]_n n5 spi4m_id[9]_p m5 spi4m_idclk_n r1 spi4m_idclk_p p1 spi4m_isclk_n ac1 spi4m_isclk_p ab1 spi4m_isclk_t ad3 spi4m_ista[0]_n ac3 spi4m_ista[0]_p ab3 spi4m_ista[1]_n ac2 spi4m_ista[1]_p ab2 spi4m_ista_t0 ac4 function pin table 1 idt88k8483 pinout (part 11 of 19) 20 of 162 october 20, 2006 idt idt88k8483 spi4m_ista_t1 ad4 spi4m_lvdsta af5 spi4m_rclk af3 spi4m_vref ad2 spien e3 tck m6 tdi w21 tdo n6 testse j21 timebase ae4 tms h21 trstb v21 wrb b5 vdda25 aa17 vdda25 aa10 vdda25 f17 vdda25 f10 vdda25 g17 vdda25 g10 vdda25 l8 vdda25 l7 vdda25 u8 vdda25 u7 vdda25 y17 vdda25 y10 vddc12 h17 vddc12 h16 vddc12 h15 vddc12 h14 vddc12 h13 vddc12 h12 vddc12 h11 vddc12 h10 vddc12 h9 vddc12 h19 vddc12 h18 vddc12 j17 function pin table 1 idt88k8483 pinout (part 12 of 19) 21 of 162 october 20, 2006 idt idt88k8483 vddc12 j16 vddc12 j15 vddc12 j14 vddc12 j13 vddc12 j12 vddc12 j11 vddc12 j10 vddc12 j9 vddc12 j19 vddc12 j18 vddc12 k10 vddc12 k9 vddc12 k19 vddc12 k18 vddc12 l10 vddc12 l9 vddc12 l19 vddc12 l18 vddc12 m10 vddc12 m9 vddc12 m19 vddc12 m18 vddc12 n10 vddc12 n9 vddc12 n19 vddc12 n18 vddc12 p10 vddc12 p9 vddc12 p19 vddc12 p18 vddc12 r10 vddc12 r9 vddc12 r19 vddc12 r18 vddc12 t10 vddc12 t9 vddc12 t19 function pin table 1 idt88k8483 pinout (part 13 of 19) 22 of 162 october 20, 2006 idt idt88k8483 vddc12 t18 vddc12 u10 vddc12 u9 vddc12 u19 vddc12 u18 vddc12 v17 vddc12 v16 vddc12 v15 vddc12 v14 vddc12 v13 vddc12 v12 vddc12 v11 vddc12 v10 vddc12 v9 vddc12 v19 vddc12 v18 vddc12 w17 vddc12 w16 vddc12 w15 vddc12 w14 vddc12 w13 vddc12 w12 vddc12 w11 vddc12 w10 vddc12 w9 vddc12 w19 vddc12 w18 vddh15 m26 vddh15 ae26 vddh15 b26 vddh15 m20 vddh15 n20 vddh15 v20 vddh15 w20 vddh15 y20 vddh25 g19 vddh25 y19 function pin table 1 idt88k8483 pinout (part 14 of 19) 23 of 162 october 20, 2006 idt idt88k8483 vddl12 aa13 vddl12 aa12 vddl12 f13 vddl12 f12 vddl12 g13 vddl12 g12 vddl12 m8 vddl12 m7 vddl12 n8 vddl12 n7 vddl12 y13 vddl12 y12 vddl25 aa14 vddl25 aa9 vddl25 aa8 vddl25 aa18 vddl25 f14 vddl25 f9 vddl25 f8 vddl25 f18 vddl25 g14 vddl25 g9 vddl25 g8 vddl25 g18 vddl25 h8 vddl25 h7 vddl25 p8 vddl25 p7 vddl25 v8 vddl25 v7 vddl25 w8 vddl25 w7 vddl25 y14 vddl25 y9 vddl25 y8 vddl25 y18 vddt33 a25 function pin table 1 idt88k8483 pinout (part 15 of 19) 24 of 162 october 20, 2006 idt idt88k8483 vddt33 a2 vddt33 af25 vddt33 af2 vss aa7 vss aa6 vss ab24 vss ae25 vss ae2 vss b25 vss b2 vss e6 vss e5 vss f7 vss f6 vss f5 vss g7 vss g6 vss h6 vss j6 vss k17 vss k16 vss k15 vss k14 vss k13 vss k12 vss k11 vss k6 vss l17 vss l16 vss l15 vss l14 vss l13 vss l12 vss l11 vss l6 vss m17 vss m16 function pin table 1 idt88k8483 pinout (part 16 of 19) 25 of 162 october 20, 2006 idt idt88k8483 vss m14 vss m11 vss n17 vss n16 vss n12 vss n11 vss p17 vss p16 vss p11 vss r17 vss r16 vss r13 vss r11 vss t17 vss t16 vss t15 vss t14 vss t13 vss t12 vss t11 vss t6 vss u17 vss u16 vss u15 vss u14 vss u13 vss u12 vss u11 vss u6 vss v6 vss w6 vss y7 vss y6 vss m25 vss aa16 vss aa11 vss f16 function pin table 1 idt88k8483 pinout (part 17 of 19) 26 of 162 october 20, 2006 idt idt88k8483 vss f11 vss g16 vss g11 vss k8 vss k7 vss t8 vss t7 vss y16 vss y11 vss k20 vss l20 vss p20 vss aa20 vss aa19 vss f20 vss f19 vss aa15 vss f15 vss g15 vss j8 vss j7 vss r8 vss r7 vss y15 vss ae1 vss b1 vss u21 vss m13 vss m12 vss r12 vss p12 vss p14 vss p15 vss n13 vss n15 vss m15 vss r14 function pin table 1 idt88k8483 pinout (part 18 of 19) 27 of 162 october 20, 2006 idt idt88k8483 vss r15 vss n14 vss p13 vtt075 g20 vtt075 h20 vtt075 j20 vtt075 r20 vtt075 t20 vtt075 u20 np 1 a1 np 1 a26 np 1 af1 np 1 af26 function pin table 1 idt88k8483 pinout (part 19 of 19) 28 of 162 october 20, 2006 idt idt88k8483 pin description table the following table lists the functions of the pins provided on the idt88k8483. some of the functions listed are multiplexed on to the same pin. the active polarity of a signal is defi ned using a suffix. analog signals ending with ?p? are defined as being positive. analog signals ending with ?n? are defined as being negative. digi tal signals ending with ?b? are def ined as being active, or asserted, when at a logic zero ( low) level. all other digital signals (including clocks, buses, and select li nes) will be interpreted as being active , or asserted, when at a logic one (high ) level. symbol 1 i/o type 2 function comments spi-4 interface link phy spi4a_ed[15:0]_p spi4b_ed[15:0]_p spi4m_ed[15:0]_p spi4a_ed[15:0]_n spi4b_ed[15:0]_n spi4m_ed[15:0]_n o lvds egress data bus. this data bus is used to carry egress payload data and in-band control words. tdat[15:0] rdat[15:0] spi4a_edclk_p spi4b_edclk_p spi4m_edclk_p spi4a_edclk_n spi4b_edclk_n spi4m_edclk_n o lvds egress data clock. this clock is associated with the egress data bus (ed) and the control signal (ectl). tdclk rdclk spi4a_ectl_p spi4b_ectl_p spi4m_ectl_p spi4a_ectl_n spi4b_ectl_n spi4m_ectl_n o lvds egress control. this signal is high when a control word is present on the egress data bus (ed) and it is low otherwise. tctl rctl spi4a_esta[1:0]_p spi4b_esta[1:0]_p spi4m_esta[1:0]_p spi4a_esta[1:0]_n spi4b_esta[1:0]_n spi4m_esta[1:0]_n i lvds egress fifo status lvds. these signals are used to carry egress round-robin fifo status information, along with associated error detec- tion and framing. tstat[1:0] rstat[1:0] spi4a_esclk_p spi4b_esclk_p spi4m_esclk_p spi4a_esclk_n spi4b_esclk_n spi4m_esclk_n i lvds egress status clock lvds. this clock is associated with the egress fifo status signals (esta). tsclk rsclk spi4a_esta_t[1:0] spi4b_esta_t[1:0] spi4m_esta_t[1:0] ilvttl pull-up egress fifo status lvttl. these signals are used to carry egress round-robin fifo status information, along with associated error detec- tion and framing. tstat[1:0] rstat[1:0] spi4a_esclk_t spi4b_esclk_t spi4m_esclk_t ilvttl pull-up schmitt trigger egress status clock lvttl. this clock is associated with the egress fifo status signals (esta_t). tsclk rsclk table 2 pin description (part 1 of 5) 29 of 162 october 20, 2006 idt idt88k8483 spi4a_id[15:0]_p spi4b_id[15:0]_p spi4m_id[15:0]_p spi4a_id[15:0]_n spi4b_id[15:0]_n spi4m_id[15:0]_n i lvds ingress data bus. this data bus is used to carry ingress payload data and in-band control words. rdat[15:0] tdat[15:0] spi4a_idclk_p spi4b_idclk_p spi4m_idclk_p spi4a_idclk_n spi4b_idclk_n spi4m_idclk_n i lvds ingress data clock. this clock is associated with the ingress data bus (id) and the control signal (ictl). rdclk tdclk spi4a_ictl_p spi4b_ictl_p spi4m_ictl_p spi4a_ictl_n spi4b_ictl_n spi4m_ictl_n i lvds ingress control. this signal is high when a control word is present on the ingress data bus (id) and it is low otherwise. rctl tctl spi4a_ista[1:0]_p spi4b_ista[1:0]_p spi4m_ista[1:0]_p spi4a_ista[1:0]_n spi4b_ista[1:0]_n spi4m_ista[1:0]_n o lvds ingress fifo status lvds. these signals are used to carry ingress round-robin fifo status information, along with associated error detec- tion and framing. rstat[1:0] tstat[1:0] spi4a_isclk_p spi4b_isclk_p spi4m_isclk_p spi4a_isclk_n spi4b_isclk_n spi4m_isclk_n o lvds ingress status clock lvds. this clock is associated with the ingress fifo status signals (ista). rsclk tsclk spi4a_ista_t[1:0] spi4b_ista_t[1:0] spi4m_ista_t[1:0] olvttl pull-up ingress fifo status lvttl. these signals are used to carry ingress round-robin fifo status information, along with associated error detec- tion and framing. rstat[1:0] tstat[1:0] spi4a_isclk_t spi4b_isclk_t spi4m_isclk_t olvttl pull-up schmitt trigger ingress status clock lvttl. this clock is associated with the ingress fifo status signals (ista_t). rsclk tsclk spi4a_bias spi4b_bias spi4m_bias analog bias. this signal must be connected via an external pull-down 1% 3k resistor to vss. spi4a_vref spi4b_vref spi4m_vref analog ref. these signals are reference for lvds. these signals should be connected to vddl12. spi4a_lvdssta spi4b_lvdssta spi4m_lvdssta icmos pull-down status channel control. this signal controls the status signal i/o type. a hardware reset or software reset must be perform after changing the level of this signal. 1 - lvds status. 0 - lvttl status. qdr-ii interface / generic interface (auxiliary interface) qdr_a[17:0] o hstl qdr_a[17:0] is qdr-ii addres s bus. this bus is used to transfer the address to the qdr-ii / fpga devices. it is driven out on the rising edge of k and k clocks during write or read operation. symbol 1 i/o type 2 function comments table 2 pin description (part 2 of 5) 30 of 162 october 20, 2006 idt idt88k8483 qdr_d[35:0]/ g_ectl[3:0], g_edat[31:0] o hstl qdr_d[35:0] is qdr-ii output data bus. this bus is used to transfer the data to the qdr-ii / fpga devices. it is driven out on the rising edge of k and k clocks during write operation. g_ectl[3:0] is generic interface egress control bus. g_edat[31:0] is generic interface egress data bus. qdr_q[35:0]/ g_ictl[3:0], g_idat[31:0] i hstl qdr_q[35:0] is qdr-ii input data bus. this bus is used to transfer data from the qdr-ii / fpga devices. it is sampled on the rising edge of k and k clocks during read operation. g_ictl[3:0] is generic interface ingress control bus. g_idat[31:0] is generic interface ingress data bus. qdr_rb o hstl qdr_rb is qdr-ii read control. th is active low signal is driven out on the rising edge of k clock. when it active, a read operation is initiated. when it deasserted, the read port is deselected. qdr_wb o hstl qdr_wb is qdr-ii write control. this active low signal is driven out on the rising edge of k clock. when it asserted, a write operation is initi- ated. when it deasserted, the write port is deselected. qdr_k / g_eclkp o hstl qdr_k is qd r-ii positive output clock. the rising edge of qdr_k is used to capture input data to the device and to drive out data from the device. g_eclkp is generic interfac e positive egress clock. qdr_kb / g_eclkn o hstl qdr_kb is qdr-ii negative output clock. the rising edge of qdr_kb is used to capture input data to the device and to drive out data from the device. g_eclkn is negative generic interface egress clock. qdr_cq / g_iclkp i hstl qdr_cq is qdr-ii synchr onous positive input clock. the rising edge of qdr_cq is tightly matched to the data inputs and can be used as a data valid indication. g_iclkp is generic interface positive ingress clock. qdr_cqb / g_iclkn i hstl qdr_cqb is qdr-ii synchronous negative input clock. the rising edge of qdr_cqb is tightly matched to the data inputs and can be used as a data valid indication. g_iclkn is generic interface negative ingress clock. qdr_vref / g_vref i analog reference qdr_vref is 0.75 reference voltage input. this static input is used to set reference level for hstl inputs and outputs as well as ac measure- ment points. this pin should be connected to v ddh15 /2. g_vref is 0.75 reference voltage input. this pin should be con- nected to v ddh15 /2. qdr_imp / g_imp i reference qdr_imp is reference input. this signal must be connected via an external pull-down 10 0 ohm resistor to vss. g_imp is reference input. this signal must be connected via an exter- nal pull-down 100 oh m resistor to vss. microprocessor interface adr[5:0] i cmos adr[5:0] is microprocessor address bus. this bus is used to transfer the address from the micro-controller. dat[7:0] / sdo i/o cmos dat[7:0] is microprocessor data bus. this bus is used to transfer the data between the device and the microprocessor. sdo (dat[0]) is serial peripheral interface (spi) data. symbol 1 i/o type 2 function comments table 2 pin description (part 3 of 5) 31 of 162 october 20, 2006 idt idt88k8483 wrb/sdi i cmos pull-up schmitt trigger wrb is microprocessor write control. active low. sdi is serial peripheral interface (spi) chip select. active low. rdb / sclk i cmos pull-up schmitt trigger rdb is microprocessor read control. active low. sclk is serial peripheral interface (spi) clock. csb i cmos pull-up schmitt trigger csb is microprocessor chip select. active low. intb o cmos open drain intb is microprocessor interrupt. active low. spien i cmos pull-up spien is serial peripheral interface (spi) mode enable. active high. mpm i cmos pull-up mpm is microprocessor mode control. this signal controls the micro- controller mode. 1 - intel mode. 0 - motorola mode. jtag interface trstb i cmos pull-up jtag reset. this active low signal asynchronously resets the boundary scan logic and the jtag tap controller. an external pull-up on the board is recommended to meet the jtag specification in cases where the tester can access this signal. tck i cmos pull-up schmitt trigger jtag clock. this is an input test clock used to clock the shifting of data into or out of the boundary scan logic or jtag controller. tms i cmos pull-up jtag mode. the value on this signal controls the test mode select of the boundary scan logic or jtag controller. tdo o cmos tri-state jtag data output. this is the serial data shifted out from the boundary scan logic or jtag controller. tdi i cmos pull-up jtag data input. this is the serial data input to the boundary scan logic or jtag controller. miscellaneous interface resetb i cmos pull-down hardware reset. active low. testse i cmos pull-down test scan enable. active high. input used for idt factory test. this sig- nal should be pulled down for normal operation. timebase i/o cmos pull-up time base. a positive edge on this signal updates the pmon counters. subsequent edges within approximately 4ms are be ignored. gpio[2:0] i/o cmos pull-up general purpose i/o . these pins can be configured as general purpose i/o pins. clock interface spi4a_rclk spi4b_rclk spi4m_rclk icmos pull-up schmitt trigger interface a/b/m reference clock. div4 i cmos pull-up pre-scalar select. configuration pin. symbol 1 i/o type 2 function comments table 2 pin description (part 4 of 5) 32 of 162 october 20, 2006 idt idt88k8483 spi4a_clk_sel spi4b_clk_sel spi4m_clk_sel icmos pull-up clock select. configuration pin. power supply and ground vddc12 pwr 1.2v core digital power supply. 76 pins total vddl12 pwr 1.2v digital power supply for lvds. 12 pins total vddh15 pwr 1.5v digital power supply for hstl. 8 pins total vddl25 pwr 2.5v digital power supply for lvds. 24 pins total vddh25 pwr 2.5v digital power supply foe hstl. 2 pins total vddt33 pwr 3.3v digital power supply for lvttl. 4 pins total vdda25 pwr 2.5v analog power supply. 12 pins total vtt075 i/o these pins are used for termination. 6 pins total vss pwr digital and analog ground. 111 pins total bond[1:0] io these pins must be connected to ground 2 1. in table 2 pin description the external pins with multiple func tions have both symbols in the symbol column (column 1). in tabl e1 idt 88k8483 pinout t he external pins with multiple functions have only the first sym bol in the function column (column 1). 2. all lvds pins have 100 internal termination resistor. symbol 1 i/o type 2 function comments table 2 pin description (part 5 of 5) 33 of 162 october 20, 2006 idt idt88k8483 functional description the idt88k8483 device is a three port spi exchange device intended for use in ethernet transport, sonet/sdh line cards, securit y firewalls, and multi-service switches. the spi-4 interface is defined by the optical internetworking forum. the device can be used to provide rate adap tation, switching, aggregation and fragment to packet conversion between network pro cessor units, multi-gigabit macs, framers and swit ch fabric interface devices. a set of hstl pi ns may be configured as a packet bus to an fpg a or as a qdr-ii memory bus. the fpga interface can be used to reduce the unnec essary overhead generated in the fpga by a spi-4 standard interfa ce. qdr-ii memory can be added as an expansion of inte rnal memory provided in the device. data path in normal operation, there are two paths through the idt 88k8483 device: the spi-4a or spi-4b ingress to spi-4m egress path , and the spi-4 m ingress to spi-4a and spi-4b egress path. spi-4 burst sizes ar e separately configurable for each physical port. data enter in bursts on a spi-4 ingress interface and are sent to the spi-4 ingress port buffe rs. the bursts are mapped to a spi-4 address and stored in the bu ffer segment pool by the packet fragment processor (pfp). the pfp forward the data to t he spi-4 egress port buffer. the content of the egress port b uffer is transferred to the spi-4 egress interface and transmitted out in burst. in addition to the data path described abov e, there are additional datapaths among the spi -4 ports, fpga interface, and microp rocessor. each spi-4 interface has the ability to perform a per-lp loopback. in addition, the spi-4a and spi-4b interfaces can transfer packet bursts on a per-lp basis. all the spi-4 interfaces can transfer packet bursts to the fpga interface on a per-lp basis. each spi-4 ingress lp (logical port) can be mapped through li d (logical identifier) to each one of the spi-4 egress lps figure 2 general data path data structure pfp structure there are 4 pfps (packet fragment processor) in the device - one per each port and dire ction. for example, for spi-4a ingress t o spi-4m egress there is one pfp. each pfp has 508 segments, and each segment has 256 bytes as shown in figure 3 pfp structure example p.34 . the user can program the lid allocation in the pfp to allocate the 508 segments to the lids that will be active. for example, the u ser can have 64 lids, and allocate 7 segments (1,792) bytes to each lid as shown in figure 4 pfp allocation example p.34 . spi-4 ingress port buffer spi-4 egress port buffer buffer segment pool (pfp) spi-4 ingress interface spi-4 egress interface idt88k8483 34 of 162 october 20, 2006 idt idt88k8483 figure 3 pfp structure example figure 4 pfp allocation example qdr-ii external memory structure the device can be connected to 18m bits qdr- ii (2m usable data bytes) sram which can st ore up to 8k segments of 256 bytes as sh own in figure 5 qdr-ii sram structure example p.34 . the user can program the lid allocation in the qdr-ii. for example, the user can have 64 lids, and allocate 128 segments (32k bytes) to each lid as shown in figure 6 qdr-ii allocation example p.34 . figure 5 qdr-ii sram structure example figure 6 qdr-ii allocation example segment 507 segment 1 segment 0 pfp (508 segments, 127k bytes) . . . 256bytes lid 63 lid 1 lid 0 pfp (508 segments, 127k bytes) . . . 7 segments (1,792 bytes) segment 8k-1 segment 1 segment 0 qdr-ii (8k segments, 2m bytes, 16m bits) . . . 256bytes lid 63 lid 1 lid 0 qdr-ii (8k segments, 2m bytes, 16m bits) . . . 128 segments / 32k bytes 35 of 162 october 20, 2006 idt idt88k8483 spi-4 ingress port buffer structure each spi-4 physical port in the ingress directi on has 32 port buffers of 128 bytes as shown in figure 7 spi-4 ingress port buffer structure p.35 . the buffers can be concatenated so that data flows from one fifo into the next. figure 7 spi-4 ingress port buffer structure flow control spi-4 ingress flow control there are 3 main parameters for configur ing the spi-4 ingress flow control: - maximum number of segments per lid is configured in m field in the pfp buffer segment assign table (p. 120) - starving free segments per lid is co nfigured in thr_starv field in the pfp buffer segment assign table (p. 120) - hungry free segments per lid is conf igured in thr_hung field in the pfp buffer segment assign table (p. 120) spi-4 ingress flow control is described in greater detail in pfp flow control (p. 53) spi-4 egress flow control there are three lid status modes in the spi-4 egress interface: starving, hungry and satisfied. in normal operation the spi-4 e gress interface is receiving starving status from the adjac ent device through the status bus, so the lid status is starving, and the lid data is s cheduled out in round robin. when the spi-4 egress interface starts receiving hungry st atus from the adjacent device, the lid status is changed to hu ngry, and the lid data is scheduled out in round robin. when the spi-4 egress interface st arts receiving satisfied status from the adjacent device, th e lid status is changed to satisfied, and the lid data is not scheduled out. each spi-4 interface has four spi-4 cal endars: two for ingress and two for egress. on ly one calendar in each direction is activ e in a specific time. there are 64 lids per pfp, and each calendar has maximum of 256 entries. each calendar entry can be assign to a specific lid as shown in figure 8 spi-4 egress calendar example p.36 . according to the calendar order, the lids with starving status are scheduled in a round robin fashion with high priority, and the lids with hungry status are scheduled in a round robin fashi on with low priority. all the lids with the starving status are scheduled first. the lids with the hungry status are scheduled only when ther e are no lids with starving status. the lid status mode in the spi-4 egress interface (status or credit mode) is configured by credit_en field in the pfp flow control register (p. 125) . if status mode is used (credit_en=0), then data is sent out until the lid status is changed (starving / hungry / satisfied). if credit mode is used (credit_en=1), then when the credit is o ne, the device sends out one data burst, clears to zero the cred it, and then waits for another credit from the spi-4 interface status bus before issuing another lid burst. in credit mode, when the spi-4 egress interface receives starving status or hungry status from the adjacent device through the status bus, it se ts the lid credit to one. when the spi-4 egress interface receives satisfied status fr om the adjacent device, it clears the lid credit to zero. buffer 30 buffer 1 buffer 0 spi-4 ingress port buffer (32 x 128 byte fifos, 4k bytes, 16k segments) . . . 128 bytes buffer 31 36 of 162 october 20, 2006 idt idt88k8483 figure 8 spi-4 egress calendar example data path detailed description there are several data paths in the dev ice as shown in the figures below. there are four pfps in the device: pfp module a tributary to ma in (pfp-a-mt), pfp module a main to tributary (pfp-a-mt), pfp mo dule b trib- utary to main (pfp-b-mt) and pfp modu le b main to tributary pfp-b-mt. spi-4 tributary to spi-4 main data path conveys data from spi -4 tributary ingress to spi-4 main egress as shown in figure 9 spi-4 tributary to spi-4 main data path p.36 . figure 9 spi-4 tributary to spi-4 main data path spi-4 main to spi-4 tributary data path conveys data from spi-4 main ingress to spi-4 tributary egress as shown in figure 10 spi-4 main to spi-4 tributary data path p.37 . lid 4 (hungry) lid 6 (starving) lid 5 (hungry) calendar (256 entries) lid 1 (starving) lid 0 (starving) entry 0 entry 1 entry 2 entry 3 entry 255 . . . spi-4a interface packet fragment processor a-tm (pfp) spi-4b interface spi-4m interface main spi-4s spi-4 egress microprocessor internal traffic detector generator internal traffic spi-4 egress auxiliary interface tributary spi-4s packet fragment processor a-mt (pfp) spi-4 egress microprocessor spi-4 egress port buffers spi-4 egress spi-4 egress microprocessor spi-4 egress microprocessor spi-4 egress port buffers spi-4 ingress packet fragment processor b-tm (pfp) packet fragment processor b-mt (pfp) spi-4 egress auxiliary interface spi-4 egress port buffers spi-4 ingress spi-4 egress port buffers spi-4 egress spi-4 egress port buffers spi-4 ingress spi-4 egress port buffers spi-4 egress spi-4 egress port buffers spi-4 ingress spi-4 egress port buffers spi-4 egress 37 of 162 october 20, 2006 idt idt88k8483 figure 10 spi-4 main to spi-4 tributary data path pfp loop data path is sending data from pfp-a back to pfp-a or sending data from pfp-b ba ck to pfp-b as shown in figure 11 pfp loop data path p.37 . figure 11 pfp loop data path figure 12 microprocessor, auxiliary and internal traffic detector/generator data path p.38 describes the following data paths: - microprocessor data path is sending data from /to microprocessor interface to/from pfp-a . - auxiliary data path is sending data from /to auxiliary interface to/from pfp-b . - internal traffic generator / detector data path is sending data fr om internal traffic generator to pfp-b and from pfp-b to i nternal traffic detector. the internal traffic generator and the internal traffic detector both use a pseudo random bit sequence (prbs) pattern. spi-4a interface packet fragment processor a-tm (pfp) spi-4b interface spi-4m interface main spi-4s spi-4 egress microprocessor internal traffic detector generator internal traffic spi-4 egress auxiliary interface tributary spi-4s packet fragment processor a-mt (pfp) spi-4 egress microprocessor spi-4 egress port buffers spi-4 egress spi-4 egress microprocessor spi-4 egress microprocessor spi-4 egress port buffers spi-4 ingress packet fragment processor b-tm (pfp) packet fragment processor b-mt (pfp) spi-4 egress auxiliary interface spi-4 egress port buffers spi-4 ingress spi-4 egress port buffers spi-4 egress spi-4 egress port buffers spi-4 ingress spi-4 egress port buffers spi-4 egress spi-4 egress port buffers spi-4 ingress spi-4 egress port buffers spi-4 egress spi-4a interface packet fragment processor a-tm (pfp) spi-4b interface spi-4m interface main spi-4s spi-4 egress microprocessor internal traffic detector generator internal traffic spi-4 egress auxiliary interface tributary spi-4s packet fragment processor a-mt (pfp) spi-4 egress microprocessor spi-4 egress port buffers spi-4 egress spi-4 egress microprocessor spi-4 egress microprocessor spi-4 egress port buffers spi-4 ingress packet fragment processor b-tm (pfp) packet fragment processor b-mt (pfp) spi-4 egress auxiliary interface spi-4 egress port buffers spi-4 ingress spi-4 egress port buffers spi-4 egress spi-4 egress port buffers spi-4 ingress spi-4 egress port buffers spi-4 egress spi-4 egress port buffers spi-4 ingress spi-4 egress port buffers spi-4 egress 38 of 162 october 20, 2006 idt idt88k8483 figure 12 microprocessor, auxiliary and inte rnal traffic detector/generator data path pfp redirect data path conveys data from pfp-a to pfp-b or from pfp-b to pfp-a as shown in figure 13 pfp redirect data path p.38 . figure 13 pfp redirect data path spi-4a interface packet fragment processor a-tm (pfp) spi-4b interface spi-4m interface main spi-4s spi-4 egress microprocessor internal traffic generator internal traffic spi-4 egress auxiliary interface tributary spi-4s packet fragment processor a-mt (pfp) spi-4 egress microprocessor spi-4 egress port buffers spi-4 egress spi-4 egress microprocessor spi-4 egress microprocessor spi-4 egress port buffer spi-4 ingress packet fragment processor b-tm (pfp) packet fragment processor b-mt (pfp) spi-4 egress auxiliary interface spi-4 egress port buffers spi-4 ingress spi-4 egress port buffers spi-4 egress spi-4 egress port buffers spi-4 ingress spi-4 egress port buffer spi-4 egress spi-4 egress port buffer spi-4 ingress spi-4 egress port buffer spi-4 egress detector spi-4a interface packet fragment processor a-tm (pfp) spi-4b interface spi-4m interface main spi-4s spi-4 egress microprocessor internal traffic detector generator internal traffic spi-4 egress auxiliary interface tributary spi-4s packet fragment processor a-mt (pfp) spi-4 egress microprocessor spi-4 egress port buffers spi-4 egress spi-4 egress microprocessor spi-4 egress microprocessor spi-4 egress port buffers spi-4 ingress packet fragment processor b-tm (pfp) packet fragment processor b-mt (pfp) spi-4 egress auxiliary interface spi-4 egress port buffers spi-4 ingress spi-4 egress port buffers spi-4 egress spi-4 egress port buffers spi-4 ingress spi-4 egress port buffers spi-4 egress spi-4 egress port buffers spi-4 ingress spi-4 egress port buffers spi-4 egress 39 of 162 october 20, 2006 idt idt88k8483 external interfaces the external interfaces provided on the idt88k8483 device ar e three spi-4 interfaces, spi-4a, spi-4b and spi-4m, an interfac e to either a fpga or a qdr-ii bus, a pin-selectable seri al or parallel microprocessor interface, a jtag interface, and five general purpose input or output (gpio) pins. the following information contains a set of the highlights of the features su pported from the relevant standards, and a d escription of additional features implemented to enhance the usability of these interfaces for the system architect. spi-4a and spi-4b refer to the oif spi-4 implementation agreement (oif-spi-4-02.1) for full details. ? two instantiations of the spi-4 interface ? clock rate is 77.76 - 450 mhz ddr ? link and phy interfaces are supported ? logical port address range of 0 ? 255 with support fo r between 1 and 64 simultaneously active logical ports ? maxburst parameters confi gurable from 16 to 256 bytes in 16 byte multiples ? 256-entry fifo status calendar ? quarter-clock-rate lvttl, or full-rate lvds fifo status signals are selectable per spi-4 port spi-4m refer to the oif spi-4 implementation agreem ent (oif-spi-4-02.1) for full details. ? one instantiation of the spi-4 main interface ? clock rate is 87 - 450 mhz ddr ? link and phy interfaces are supported ? logical port address range of 0 ? 255 with support fo r between 1 and 128 simultaneously active logical ports ? maxburst parameters confi gurable from 16 to 256 bytes in 16 byte multiples ? 256-entry fifo status calendar ? quarter-clock-rate lvttl, or full-rate lvds fifo status signals are selectable per spi-4 port fpga interface the fpga interface is shared with the qdr-ii interface. se lecting the fpga interface enables the following features: ? clock rate is 160 - 200 mhz ddr source-synchronous ? logical port address range of 0 ? 63 with s upport for 64 simultaneously active logical ports ? ddr hstl logic levels qdr-ii interface the qdr-ii interface is shared with the fpga interface. se lecting the qdr-ii interface enables the following features: ? clock rate is 160 - 200 mhz qdr-ii ? up to 18 mbit of qdr-ii memory is supported ? qdr-ii hstl logic levels microprocessor interface parallel microprocessor interface: ? eight bit data bus ? six bit address bus ? pin-selectable intel or motorola control signals ? direct accessed space used for quick interrupt processing ? expanded indirect access space used for provisioning ? read operations to a reserved address or reserved bit fields return 0 ? write operations to reserved addr esses or bit fields are ignored 40 of 162 october 20, 2006 idt idt88k8483 serial microprocessor interface: ? compliance to motorola serial peri pheral interface (spi) specification ? byte access ? direct accessed space used for quick interrupt processing ? expanded indirect access space used for provisioning ? read operations to a reserved address or reserved bit fields return 0 ? write operations to reserved addr esses or bit fields are ignored jtag ? complies with the ieee 1149.1 standard. gpio ? three gpio signals are provided. each signal ma y be independently defined as an input or an output pin. ? the gpio interface allows flexible use of the gpio pins. the following can be defined per gpio pin: direction: input or output level: value to write if programmed to be an output, or value that is being read if programmed to be an input 41 of 162 october 20, 2006 idt idt88k8483 spi-4 interface overview spi-4.2 as originally defined is an interface for packet and ce ll transfer between a physical layer (phy) device and a link lay er device (network processor), for aggregate bandwidths of oc-192 atm and packet over so net/sdh (pos), as well as 10 gb/s ethernet applications. t he spi-4.2 protocol transfers data in variable length bur sts. associated with each burst is inform ation such as logical port number (for a multi-port device such as a 10 x 1 gbe mac), sop, eop. this information is collected by the spi-4 interface and passed to the pfps. the optical internetw orking forum (oif) controls the spi-4.2 implementation agreement document (available at http://www.oiforum.com). the spi-4 interface power down mode has to be disabled before configuring the interface. the spi-4 interface also has to be con figured before the interface is enabled. the spi-4 interface lvds outputs (except fo r the clock) can be powered down by setting to 1 the spi4_pdn field in the spi-4 interface enable register (p. 106) . the interface is enabled by setting to 1 the spi4_en field in the spi-4 interface enable register (p. 106) . the spi-4 interface consists of separate i ngress and egress interfaces as described in figure 14 idt88k8483 spi-4 connections example p.42 . the ingress and egress ports are unidire ctional and independent of each other. each port has 16 data signals, a clock, and a control signal, all of which use lvds (differential) signaling, and are sampled on both edges of the clock. there are also ingress stat us port and egress status port. each status port has 2 fifo status signals and a clock. the status port signal can be configured to lvds (differential) o r lvttl by the status channel control pin lvdssta (spi4a_lvdssta, spi 4b_lvdssta, spi4am_lvdssta) . the ingress port supports dy namic alignment, and the egress port supports programmable skew. the idt88k8483 has three spi-4 interfaces: one main spi-4 interfac e (m) and two tributary spi-4 interface (a and b). each tribu tary spi4 inter- face supports up to 64 logical ports. the main spi4 interface supports up to 128 logical ports. the logical port in-band addres s are from 0 to 255. the clock source for the spi-4 ingress por t is the spi-4 interface input clock idclk (spi4a_idclk_p, spi4a_idclk_n, spi4b_idclk _p, spi4b_idclk_n, spi4m_idclk_p and spi4m_idclk_n). the source cloc k for the spi-4 egress port is the internal spi-4 clock generat or. 42 of 162 october 20, 2006 idt idt88k8483 figure 14 idt88k8483 spi-4 connections example spi-4 ingress data channel the spi-4 ingress data channel is independent from the status channel. the data channel supports bit alignment and de-skew, err or event detec- tion and transfer termination. the stat us channel generates status frame, and controls the output skew per lane. idt88k8483 network processor spi4a_ed[15:0]_p spi4a_ed[15:0]_n spi4a_edclk_p spi4a_edclk_n spi4a_ectl_p spi4a_ectl_n spi4a_esta[1:0]_p spi4a_esta[1:0]_n spi4a_vref spi4a_bias 3k 1% v ddl12 spi4a_id[15:0]_p spi4a_id[15:0]_n spi4a_idclk_p spi4a_idclk_n spi4a_ictl_p spi4a_ictl_n spi4a_ista[1:0]_p spi4a_ista[1:0]_n spi4a_esclk_p spi4a_esclk_n spi4a_isclk_p spi4a_isclk_n spi4a_lvdssta v ddl25 spi4a_ed[15:0]_p spi4a_ed[15:0]_n spi4a_edclk_p spi4a_edclk_n spi4a_ectl_p spi4a_ectl_n spi4a_esta[1:0]_p spi4a_esta[1:0]_n spi4a_esclk_p spi4a_esclk_n spi4a_id[15:0]_p spi4a_id[15:0]_n spi4a_idclk_p spi4a_idclk_n spi4a_ictl_p spi4a_ictl_n spi4a_ista[1:0]_p spi4a_ista[1:0]_n spi4a_isclk_p spi4a_isclk_n 43 of 162 october 20, 2006 idt idt88k8483 figure 15 spi-4 ingress block diagram bit alignment the bit alignment block is responsible fo r data and clock alignment. the bit alignment allows the clock to be used for correct data sampling and eliminate bit errors by providing adequate set-up and hold time margins. the alignment selection is progra med by auto_align field in the spi-4 ingress automatic alignment control register (p. 109) . the device is responsible for an edge transition histogram for each lane (lane is defined as a deferential pair of data, control or status si gnals). the data is sampled by 10-phased-shifted clock during each clock cycle. each 2 consecutive sampled values are xored and accumulated during a fixed observation window to generate transition edge histogram. the measurement histogram is triggered by writing to the lane field in the spi-4 histogram measur e launch register (p. 117) . the measurement process is indicated by the busy field in the spi-4 histogram measure status register (p. 117) . the busy field is set to 1 when a measurement is launched. the busy field is auto cleared to 0 when the measure is finished. the received bit stream is selected from the 10 sam ples. the tap selec- tion is made automatically and is avai lable in the tap_sel field in the spi-4 bit alignment result register (p. 118) . the bit alignment sequence automatically carried out in the device as follows: - write lane number in the lane field in the spi-4 histogram measure launch register (p. 117) . - poll the busy field in the spi-4 histogram measure status register (p. 117) . if busy is 0, then read the c[n] field in the spi-4 histogram counter register (p. 117) which indicates the counter value. the counter value is used to select the tap. - write the selected tap value to tap field in the spi-4 bit alignment result register (p. 118) . de-skew the de-skew block is responsible for alignment between the dat a signals. the de-skew block c an de-skew +/-1bit. for diagnose pu rpose, an out of range offset between lines is provided. if the skew is more than 2 bits, then the i_dsk_oor field in the spi-4 ingress status register (p. 108) is set. the i_dsk_oor field is clear ed when the offset is in range. receive state machine the ingress data channel has 2 states, in_sy nch and out_of_synch. the machine transitions from out_of_synch to in_synch if a number of consecutive error-free dip-4 are detec ted. the number is configured by using the spi-4 ingress configuration register (p. 106) . the machine stays in out_of_synch state if the interface is not enabled. the status of the synchronization is indicated by i_syncv field in the spi-4 ingress status register (p. 108) . any transition on i_syncv will be captured by the pmon event interrupt indication register (p. 136) . an interrupt is generated if interrupt options is enabled. the data channel synchro- nization status is fed to status channel generation logic for handshaking. bit alignment deskew rx machine status generation locker skew control status pfp 44 of 162 october 20, 2006 idt idt88k8483 figure 16 spi-4 ingress state machine the bus word may be payload data word, payload control word, idle c ontrol word or training word. it is classified by the ctl in put signal and the content of the control field. the dip fields of the control word prev ious and subsequent payload data or training data are subject ed to dip checking. dip che cking is performed both in in_synch and out_of_synch state. in in_synch state, eac h dip error generates a dip-4 erro r event. this event is capture d and forward to pmon. the logical port information is carried in the payload control wo rd. the following data words are associated with this logical port. the lp to lid mapping is defined by the spi-4 ingress lp to lid mapping table (p. 105) . transfers for inactive lps are flus hed, and an ingress inactive logical port event generates. the event and the associated logical port are forwarded to pmon. for each active logical port, data word, sop, eop, abort tag and length are put into associated ingress port buffer. for statisti cs purpose, the number of transfers and bytes are forwarded to pmon. multiple logical ports can not be mapped to the same lid. the logical port can not remapped in the in_synch state. errors handling scheme: when a dip4 error is received in the in in_synch state, a dip4 error event is generated and an error tag is added to the packet s being received. when a reserved control word is received, a bus erro r event is generated and the control word is ignored. when consecutive payload control words are received, a bus error event is generated and every control word is ignored except th e last received. when payload is received following an idle control word, a bus error event is generated. when a transfer belonging to an inactive lp is received, an i nactive transfer event is generated and the transfer is dropped. when an unaligned transfer is received, a bus error event is generated. spi-4 ingress associated status channel status generation the device supports both lvttl and lvds status channel mode. the status mode (lvds/lvttl) is configured by lvdssta (spi4a_lvdss ta, spi4b_lvdssta and spi4m_lvdssta) pin. the level of the lvdssta pin is reflected by lvds_sta field in the spi-4 ingress status register (p. 108) . when the device is in lvttl status mode, and if ingress data channel is out of sync, it sends all ?11?. when the device is in l vds status mode, and if ingress data channel is out of sync, it sends training pattern . when the device is in sync, it sends calendar frame or perio d training. they are switched at the frame boundary. the device supports one or two sets of calendars. if i_csw_en field in the spi4 ingress calendar switch control register (p. 109) is set to 1, then two sets of calendars are used. in this mode, a calendar se lection word must be received immediately after the framing wor d for correct opera- tion. if cal_sel field in the spi4 ingress calendar switch control register (p. 109) is cleared to 0, then the device selects calendar 0 and the selec- tion word is fixed to 01b. if cal_sel field in the spi4 ingress calendar switch control register (p. 109) is set to 1, then the device selects calendar 1, and the calendar selection word is fixed to 10b. in_synch out_of_synch a= a number of consecutive dip-4 error or reset or interface disabled or a number of consecutive training pattern received b= a number of consecutive dip-4 error free a b 45 of 162 october 20, 2006 idt idt88k8483 if the i_csw_en field is cleared to 0, then the dip-2 is computed over all preceding status indica tions after the last ?11? fra ming pattern. if i_csw_en is set to 1, and i_dip_csw is set to 1, then the dip-2 is computed over calendar selection word and all preceding s tatus indications after last ?11? framing pattern. if i_csw_en is set to 1, and i_dip_csw is set to 0, then the dip-2 is computed over all precedi ng status indications after last ?11? framing pattern and excluding the calendar selection word. the starving, hungry or satisfied indication for each status word for each logical port is based on the status from the pfp and the spi-4 ingress port buffer fill level. see spi-4 ingress watermark register (p. 111) . the calendar length is configured by the i_cal_len field in the spi-4 ingress calendar 0 configuration register. (p. 107) while calendar length=i_cal_len+1. in lvttl mode, the i_cal_len field can be progra mmed to any value. in lvds mode, the i_cal_len field must b e programmed to 4n-1 (n is an integer). output skew the lvds output lane skew is adjustable in order to provide gr eater flexibility for board layout. the clock outputs can be skew ed over a range of 0 to 0.9 clock cycles with a resolution of 0.1 clock cycle. the data outputs can be skew ed over a range of 0 to 0.3 clock cycle w ith a resolution of 0.1 clock cycle. the skews are controll ed by the output delay registers. diagnostics features - ingress data channel clock detect. the ingres s data clock idclk (spi4a_idclk_p, spi4a_idclk_n, spi4b_idclk_p, spi4b_idclk_n, spi4m_idclk_p, and spi4m_idclk_n) is monitored. if there is no transition on idclk in a 2048 mclk hopping window, then the dclk _av field in the spi-4 ingress status register (p. 108) is cleared to 0. the dclk_av flag transition from 1 to 0 generates an event towards the pmon, and the pmon captures this event. - ingress port buffer unavailable. if there is more data but no port buffer available, then the device discards the data, gener ates a spi_4 port buffer unavailable event, and forwards the event to pmon. - dip-2 error insertion. a number of consec utive (less then 16) dip-2 errors can be gene rated. the number of errors is configur ed by the dip_e_num field in the spi-4 ingress diagnostics register (p. 109) . when the i_err_ins field in the spi-4 ingress diagnostics register (p. 109) is set to 1, it triggers error insertion using the i_dip_num field value. the i_err_ins field is self cleared when the correct num ber of errors is gener- ated. the i_dip_num field value is not changed by device. - force continuous training. the status c hannel generates continuous training pattern in lvds protocol if i_force_train field i n the spi-4 ingress diagnostics register (p. 109) is set to 1. the status channel generates a continuous ?1 1? pattern in lvttl protocol if i_force_train field is set to 1. - ingress port buffer fill level. the ingress port buffer fill level is indicated in the fill_curr field in the spi-4 ingress fill level register (p. 110) . the maximum port buffer fill level is confi gured by using the fill_max field in the spi-4 ingress training to out of sync threshold register (p. 111) . spi4 egress data channel the spi4 egress interface has data channel and status channel. t he data channel carries transfers, and the status channel carri es status. the output skew is per lane controllable. the status channel does bit alignment and de-skew in lvds mode. the device receives statu s frame for control- ling the data path flow. in packet mode, the tx machine must tr ansmit a complete packet before it starts a transfer for another logical port. 46 of 162 october 20, 2006 idt idt88k8483 figure 17 spi-4 egress state block diagram tx machine control words are inserted only between the transfers. once a transfer has begun, the data words are sent uninterrupted until a whole transfer is complete. the interval between the end of a given transfer and the nex t payload control word consists of zero or more idle cont rol words and training patterns. successive sop must oc cur not less than 8 cycles apart. figure 18 egress word transition state machine p.46 shows the word transition on the interface. the adjacent device that generates the transfer have to meet the requirements as described in figure 18 egress word transition state machine p.46 . figure 18 egress word transition state machine the spi-4 interface loads data and overhead from the egress por t buffer and generates transfer. t he cycle to cycle behavior is described in figure 18 egress word transition state machine p.46 . the number of idle control words between trans fers is less than or equal to 4 if there is data for transmit. the lid to l ogical port mapping is configured by spi-4 ingress training to out of sync threshold register (p. 111) . multiple lid can not be mapped to the same logical port. lid can not be remapped in the in_synch status. packet mode and cut through mode selection is defined in pfp. the main spi-4 transmit data from module a/b in round robin. in c ut-through mode, the unit is one transfer, while in packet mode, the unit is one packet. if only one byte of the spi-4 16 bit wide data is valid, then 8 lsb (b7 to b0) are fixed to 0. status termination tx machine locker skew control bit aligne de-skew data status pfp 47 of 162 october 20, 2006 idt idt88k8483 egress associated status channel bit alignment the alignment selection is progr amed by auto_align flag in the spi-4 egress automatic alignment control register (p. 115) . the device is responsible for edge transition histogram for each lane. the data is sampled by 10-phased shifted clock during ea ch clock cycle. each consecutive pairs of sampled values are xored and accumulated during a fix ed observation window to generate transition edg e histogram. the measure histogram is triggered by writing to the lane field in the spi-4 histogram measure launch register (p. 117) . the measurement process is indicated by a busy flag in the spi-4 histogram measure status register (p. 117) . the busy field is set to 1 when a measurement is launched. the busy field is auto cleared to 0 when the measurement is finished. the status channel tap is configured by the aut o_align field in the spi-4 egress automatic alignment control register (p. 115) . the bit alignment sequence is as follows: - write lane number in the lane field in the spi-4 histogram measure launch register (p. 117) . - poll the busy field in the spi-4 histogram measure status register (p. 117) . if busy is 0, then read the c[n] field in the spi-4 histogram counter register (p. 117) which indicates the counter value. the counter value is used to select the tap. - write the selected tap value to tap field in the spi-4 bit alignment result register (p. 118) . de-skew the de-skew block can de-skew +/-1bit. for diagnostic purpose, an out of range offset between lines is provided. if deskew is m ore than 2 bits, then the e_dsk_oor field in the spi-4 egress status register (p. 115) is set. e_dsk_oor field is cleared when in range. status termination the protocol (lvds/lvttl) is configured by spi4_lvdssta input pin. the status channel has 2 states, in_synch and out_of_synch. a number of consecutive dip-2 error- free values cause a transition fr om out_of_synch to in_synch st ate. this number is configured by spi-4 egress configurati on register (p. 113) . a number of consecutive dip-2 errors will force the machine to out_of_synch state. this number is configured in the spi-4 egress configuration register (p. 113) . in lvds protocol mode, 12 consecutive ?11? will force the machine to out_of_synch state. in lvttl protocol mode, 12 consecutive ?11? will force the machine to out_of_synch state. the machine?s sta te is indi- cated by e_syncv field in the spi-4 egress status register (p. 115) . any transition on the e_syncv field is captured, and generates an interrupt if enabled. figure 19 status channel state machine the device supports one or two sets of calendars. if e_csw_en field in the spi-4 egress calendar switch control register (p. 116) is set to 1, then two sets of calendars mode are used. in this case, a ca lendar selection word must be pl aced following the framing bit. if cal_sel field in the spi-4 egress calendar switch control register (p. 116) is cleared to 0, then the device selects calendar 0, and the selec- tion word is fixed to 01b. if cal_sel field is set to 1, then the device selects calendar 1, and the selection word is fixed to 10b. in_synch a a=a number consecutive dip-2 error free b=a number of consecutive dip-2 error,training, port disabled or reset out of synch b 48 of 162 october 20, 2006 idt idt88k8483 if the e_csw_en field is cleared to 0, then the dip-2 is computed over all preceding status indica tions after last ?11? framing pattern. if e_csw_en field is set to 1, and e_dip_csw field is set to 1, then the dip-2 is computed over calendar selection word and all pr eceding status indi- cations after last ?11? framing pattern. if e_csw_en field is set to 1, and e_dip_csw field is set to 0, then the dip-2 is comp uted over all preceding status indications after last ?11? framing pattern, excluding the calendar selection word. in in_synch state, each dip-2 error generates a dip-2 error event towards to pmon. a single dip-2 error sets all calendar lp?s status to ?satis- fied?. in in_synch state, the status is updated per cycle rather than updated all lp at the end of the frame. in out_of_synch s tate, the calendar? lp?s status are fixed to ?satisfied?. in the two-calendar modes, the msb of calendar id is extracted to cal_id field in spi-4 egress calendar switch control register (p. 116) . the cal_id field does not change in single calendar mode or in out of sync state. the calendar length is configur ed in the e_cal_len field in the spi-4 egress calendar 0 configuration register (p. 114) . in lvttl mode, the e_cal_len field can be programmed with any value. in lvds mode, the e_cal_len field must be programmed with 4n-1 (n is an integ er). no status channel option there is an option to configure the device to no status channel mode by the no_stat field in the spi-4 egress configuration register (p. 113) . in no status mode, the egress synchronization is fixed at out of sync, there is no dip-2 error check, and per lp status is fixed t o ?starving?. diagnose features - egress status channel clock detect. if t here is no transition on mclk clock in a 2048 mclk hopping window, then the slck_av f ield in the spi- 4 egress status register (p. 115) is cleared to 0. the slck_av field transition from 1 to 0 generates an event forward to pmon. in lvds i/o mode, the device detects ?no transition? on the lvds input clock. - dip-4 error insertion. a number of cons ecutive (less than 16) dip-4 errors can be generated. the number of error is configure d by the e_dip_num field in the spi-4 egress diagnostics register (p. 115) . when the e_err_ins field in the spi-4 egress diagnostics register (p. 115) is set to 1, error insertion is triggered us ing the e_dip_num field val ue.the e_err_ins field is se lf cleared when the correct num ber of errors is gener- ated. the e_dip_num field value is us er-configured and is not changed internally. - force continuous training. the data channel generates continuous training patte rn if e_force_train field in the spi-4 egress diagnostics register (p. 115) is set to 1. - egress port buffer fill level. the egress port buffer fill level is indicated in the fill_cur field in the spi-4 egress fill level register (p. 116) . the maximum port buffer fill level is confi gured by using the fill_max field in the spi-4 egress max fill level register (p. 116) . insert and extract paths obc insert/extract path a useful feature for diagnostics is the obc (on board controller) insert and extract path. 49 of 162 october 20, 2006 idt idt88k8483 the obc insert and extract paths are provid ed on both directions of the packet fragment processor a. they are intended for low bandwidth communications channels like operation administr ation, maintenance functions etc. the obc insert, inserts packets into the spi4 stream via the obc insert locker which is 256 bytes and packets from the spi4 stream can be extracted via the obc extract locker which is 256 byte s. both insertion and extraction can be done on both side of pfp-a. the format for pfp insertion is as depicted in the following figure. spi 4 a spi-4 spi-4 spi-4 spi 4 b spi 4 physical port link identification spi-4 logical port spi-4 logical port physical port obc insert extract prbs auxiliary 50 of 162 october 20, 2006 idt idt88k8483 obc insert the first byte indicates the sop or eop and also whether the pa cket is error tagged or not by writing into the ed bit. the seco nd byte is the lid information, which tells the obc controller, which lid the packet goes to. the 3rd byte is the length of the packet in bytes. a fter this overhead is written, the packet is written into the obc insert locker, not to ex ceed 256 bytes. if the packet length exceeds 256 bytes, then the fir st 256 bytes is written into the locker, transferred to the pfp and when the locker is empty, t he remaining bytes of the packet is written into the insert l ocker. the pseudo code is given below. begin: is {packet_length > 256} if yes {set flag = (sop = 1 << 7) || (eop = 0)} else {set (sop = 1 << 7) || (eop = 1)} if yes {set length = 256} else { set length = packet_length} direct read data_available flag in pfp t-m insert control register (register offset=0x0) (p. 96) // availability of obc insert fifo if {result = 0} write flag into pfp t-m insert data register(register offset=0x1) (p. 97) write lid_number to pfp t-m insert data register (register offset=0x1) (p. 97) write length to pfp t-m insert data register(register offset=0x1) (p. 97) write packet_data to pfp t-m insert data register(register offset=0x1) (p. 97) //if length >256, write 256 bytes in run1. write 0x1 to pfp t-m extract control register (register offset=0x2) (p. 97) // to launch data. this causes data to be read into the pfp and //clear the fifo and setting the data_available bit to 0. if {packet_length>256} { set remaining_length = packet_length - 256 set packet_length = remaining_length goto begin } flags length data[1] data[2] data[255] lid data[0] sop ed eop not used ed packet error 70 insert sequnece t t+1 t+258 extract sequnece t t+1 t+258 51 of 162 october 20, 2006 idt idt88k8483 obc extract the obc extract process also works in the same way. the obc extract fifo can hold up to 256 bytes of data. the registers used i n this process are pfp t-m extract control register (register offset=0x2) (p. 97) and pfp t-m extract data register (register offset=0x3) (p. 97) . the pseudo code for the extract process is as follows begin: direct read pfp t-m extract control register (register offset=0x2) (p. 97) if {result = 0} return // result = 0i ndicates that the obc extract fifo is empty else read 39 set eop=result && 0x01 // the first bit of the first byte read indicates whether packet in the extract fifo is>256 bytes. read pfp t-m extract data register (register offset=0x3) (p. 97) // the second byte gives the lid info read pfp t-m extract data register (register offset=0x3) (p. 97) // the 3rd byte gives the length of the packet stored in the fifo for {i=0} {i 53 of 162 october 20, 2006 idt idt88k8483 the egress also has the flexibility to be programmed for burst or non-burst mode and status or credit mode transfer control. wh en burst_en field in the pfp flow control register (p. 125) is set to 1, the burst mode is enabled, and the same lid can transfer more than one segment of data from the data buffer to the egress port buffer. if the burst mode is not enabled, then the lid can transfer only one segment of data at a time from the data buffer to the egress port buffer, and the pfp can schedule the next segment for the lid only after the current segment has been transmitted. when credit_en field in the pfp flow control register (p. 125) sets to 1, the credit mode is enabl ed, and the device uses the lid credit. the maximum burst size can be configured separately for starving status and for hungry st atus. the maximum burst size for starv ing status is configured in the max_burst_s field in the pfp egress burst size table (p. 122) . the maximum burst size for hungr y status is configured in the max_burst_h field in the pfp egress burst size table (p. 122) . the egress can be programmed to interleave packet mode and packet m ode. the packet mode for each lid is configured by setting t o 1 the pkt_mode in the pfp egress packet mode control registers (p. 123) . in interleave mode the scheduler schedul es parts of the packet. in packet mode the scheduler schedule the whole packet. when the egress is pack et mode, and it receives back-pressure in the middle of se nding a packet, it finishes sending the current pac ket before stalling any subsequent packets queued for transmission. pfp flow control pfp ingress flow control for non over booking mode there are 3 main parameters for configuring the spi-4 ingress flow control for non over booking mode: - maximum number of segments per lid is configured in m field in the pfp buffer segment assign table (p. 120) . - starving free segments per lid is co nfigured in thr_starv field in the pfp buffer segment assign table (p. 120) . - hungry free segments per lid is conf igured in thr_hung field in the pfp buffer segment assign table (p. 120) . there are three status options per lid in the spi-4 ingress pfp: starving hungry and sa tisfied. in spi-4 ingress pfp for lp0 (f or example), in normal operation there are enough free segments, so the lid status is starving, and the spi-4 ingress interface is sending star ving status to the adja- cent device through the status bus. when the number of free segm ents is less than thr_starv (for example 100 segments), the lid status is changed to hungry, and the spi-4 ingress interface starts sending hungry status to the adjacent dev ice. when the number of free segments is less than thr_hung (for example 50 segments), the lid status is changed to satisfied, and the spi-4 ingress interface starts sending satisfied status to the adjacent device. when the number of free segments is again more than thr_hung (f or example 50 segments), the li d status is changed to hungry, an d the spi- 4 ingress interface starts sending hungry status to the adjacent device through the status bus. when the number of free segment s is again more than thr_starv (for example 100 segments), the li d status is changed to starving, and the spi-4 ingress interface starts sending sta rving status to the adjacent device. figure 21 pfp ingress flow control example according to the status information from the qdr-ii lid, the pfp lid, and the flow control mode the device generates the status indication to the spi-4 interface as shown in table 3: ?spi-4 status information? (p. 56) . the device gets the qdr-ii lid status information from the qdr-ii interface, and the pfp lid status information from the pfp logi c. the device gets the flow cont rol mode from the ebp_en field i n the pfp egress packet mode control registers (p. 123). see more information about the pfp/qdr-ii flow control in the qdr-ii flow control (p. 56) . satisfied starving satisfied pfp (508 segments, 127k bytes) starving free segments assigned to lid 0 = 100 hungry starving hungry free segments assigned to lid 0 = 50 maximum number of segments assigned to lid 0 = 256 hungry starving free segments assigned to lid 1 = 100 hungry free segments assigned to lid 1 = 50 maximum number of segments assigned to lid 1 = 256 lid 1 lid 0 54 of 162 october 20, 2006 idt idt88k8483 pfp ingress flow control for over booking mode there are 4 main parameters for configuring the pfp ingress flow control for over booking mode: - maximum number of segments per lid is configured in m field in the pfp buffer segment assign table (p. 120) . - starving free segments per lid is co nfigured in thr_starv field in the pfp buffer segment assign table (p. 120) . - hungry free segments per lid is conf igured in thr_hung field in the pfp buffer segment assign table (p. 120) . - global free segments per lid is conf igured in the buf_thr field in the pfp buffer management configuration register (p. 123) . there are three status options per lid in the spi-4 ingress pfp: starving hungry and sa tisfied. in spi-4 ingress pfp for lp0/lp 1 (for example), in normal operation there are enough free segments, so the lids stat us are starving, and the spi-4 ingress interface is sending st arving status to the adjacent device through the status bus. when the number of free s egments for each lid is less t han thr_starv (for example 400 s egments), the lid status is changed to hungry, and the spi-4 ingress interfac e starts sending hungry status to the adjacent device. when the number of free segments for each lid is less than thr_hung (for example 300 segment s), the lid status is changed to satisfied, and the spi-4 i ngress interface starts sending satisfied status to the adj acent device. when the total number of free segments for all the lids is less than bu f_thr (for example 50 segments), the status of all the lids are changed to satisfied, and the spi-4 ingress interface starts sending satisfied status to the adjacent device. figure 22 pfp flow control example for over booking mode detailed examples: example 1. lid0 gets data for 120 segments and lid2 gets data for 120 segments, so lid0 has 392 free segments and lid0 has 392 free segments. in this case, the number of free segments for lid0 is less than thr_starv (400), so lid0 sends hungry status to the a djacent device. the number of free segments for lid1 is also less than thr_star v (400), so lid1 sends hungry i ndication to the adjacent device. example 2. lid0 gets data for 220 segments and lid1 gets data fo r 220 segments, so lid0 has 292 free segments and lid1 also has 292 free segments. in this case, the number of free segments for lid0 is less than thr_hung (300), so lid0 sends satisfied status to the adjacent device. the number of free segments for lid1 is also less than thr_hung (300), so lid1 sends satisfied indication to the adjacent devic e. example 3. lid0 gets data for 250 segments and lid2 gets data for 250 segments, so the total number of occupied segments for bo th lid0 and lid1 is 500, and the total number of free segments for both lid0 and lid1 is 12. in this case, the total number of free segment s for both lid0 and lid1 is less than buf_thr (50), so lid0 and li d1 send satisfied status to the adjacent device. satisfied starving pfp (508 segments, 127k bytes) hungry starving free segments for lids 0 and 1 = 400 hungry free segments for lids 0 and 1 = 300 maximum number of segments for lids 0 and 1 = 508 global free segments for lids 0 and 1 = 50 hungry / satisfied 55 of 162 october 20, 2006 idt idt88k8483 qdr-ii interface overview the auxiliary interface has two modes: qdr-ii interface mode and generic interface mode. the auxiliary interface mode (qdr-ii o r generic) is configured by the mem field in the auxiliary interface configuration register (p. 129) . the auxiliary interface has to be configured before the interface is enabled. the auxiliary interface outputs (except for the clock) can be powered down by setting to 1 the aux_pdn field in the auxiliary interface enable register (p. 129) . the interface is enabled by setting to 1 the aux_en field in the auxiliary interface enable register (p. 129) . the qdr-ii interface can be connected to 18m bit qdr-ii burst of two sram with 36 bit data at 200 mhz. the interface has 36 bit s input data bus, 36 bits output data bus (four bytes) and 18 bits address bus. the 36 bits data bud include 32 bi ts payload data and 4 bits over head. the interface has also qdr_k and qdr_kb output clocks and qdr_cq and qdr_cqb input clocks. the device supports up to 64 independent fifos in the memory, and a full duplex 10gbps data-stream to and from the memory. it also supports flow control per lid. the qdr_vref signal should be connected to 0.75v generated from the vddh15 power supply using regulator or potential divider su ch as the max1510 as shown in figure 42 idt88k8483 vdda25 filter circuit p.75 . figure 23 idt88k8483 and idt7172604 qdr-ii sram connections qdr-ii transfer format in a single write burst a transfer with 1 to 256 bytes is stored in the memory. a format is defined to map the 1 to 256 bytes i n a proprietary transfer format. the format adds 4 overhead bits to each 32 payload bits group. the transfer format overhead includes the total length o f the payload (in units of bytes), packet delineation and error tags. the first two overhead fields of a transfe r format contain the higher bit of the transfer length, and the transfer beginning field. the thir d overhead field contains packet delineation and error tag. the fourth overhead field contain s the last two bits of the transfer length. all the remaining overhead fields are fixed to 0?b0000. the minimum length of the transfer format is 4 words (36 bit) . the payload is padded with a fixed 0xff pattern. the transfer le ngth is equal to an integer multiple of 2 words (36 bit). memory segmentation the external sram is segmented in a confi gurable number of fifos with equal size. the number of the fifos is configured by ebc field in the auxiliary interface confi guration register (p. 129) . the memory is managed based on memory segment size of 256byte. idt88k8483 idt7172604 qdr_a[17:0] qdr_d[35:0] qdr_q[35:0] d[35:0] q[35:0] sa[35:0] r qdr_rb qdr_wr qdr_k qdr_kb k k w qdr_cq qdr_vref qdr_imp qdrii sram 18mb burst of 2 qdr_cqb cq cq v ddh15 /2 100 ohm 56 of 162 october 20, 2006 idt idt88k8483 qdr-ii flow control the idt88k8483 gets the qdr-ii fifo status in formation from the qdr-ii interface, and t he pfp lid status information from the p fp logic. the idt88k8483 can be configured to one of two different fl ow control modes using the ebp_en field in the pfp egress packet mode control registers (p. 123). according to the status information from the qdr-ii fifo and the pfp lid, and the flow control mode, the device generates the status indi- cation to the spi-4 interface as shown in ta b l e 3 spi-4 status information (p. 56). if ebp_en field in the pfp egress packet mode control registers (p. 123) is 0 then the flow control mode is mode 1 - packet assembling, no back- pressure or occasional (emergency) backpressure (for example when egress is not rate limited). if ebp_en field in the pfp egress packet mode control registers (p. 123) is 1 then the flow control mode is mode 2 - buffering, frequent back- pressure (for example rate limited egress). - when the qdr-ii flow control mode is mode 1, the device sends the pfp status to the spi-4 interface. - when the qdr-ii flow control mode is mode 2, the device sends status to the spi-4 interface based on the qdr-ii status. if th e qdr-ii status is satisfied or hungry, then the device sends sa tisfied status to the spi-4 interface. if the qdr-ii status is starving, then the device sends starving status to the spi-4 interface. flow control mode 1 - packet assembling in the packet assembling option the idt88k8483 receives the data in interleaved mode and it sends the data in packet mode (non- interleave mode). in this option the pfp and the qdr-ii should be program ed to packet mode by setting to 1 the pkt_mode field in the pfp egress packet mode control registers (p. 123) and the pkt_mode field in the auxiliary packet mode conf iguration register (p. 131) . in this case, the device reas- semble the interleave data from each channel to packet by monitoring the sop and eop in dication. it starts the packet with the sop indication and ends the packet with the eop indication. the device sends the da ta in packet mode from the qdr-ii to the pfp and then to the po rt buffers and to the spi-4 interface. an application example for flow contro l mode 1 (packet mode) is described in figure 24 . in this example the device is in over-booking mode, the pfp is used only as a temporary storage, so the packets should be sent immediatel y from the pfp. therefore, there is not enough memory for sched- uling too many packets, and there cannot be fr equent back-pressure. if there is too many back pressure the storage space is lim ited, and the over- booking mode is not efficient. since in this case there is no much back-pressure, t here is no need to transfer the back-pressur e from the qdr-ii to the pfp and to the interface. therefore, the idt 88k8483 sends the pfp status to the interface. qdr-ii fifo status spi-4 interface status (flow control option 2) starving starving hungry satisfied satisfied satisfied starving starving hungry satisfied satisfied satisfied starving starving hungry satisfied satisfied satisfied table 3 spi-4 status information 57 of 162 october 20, 2006 idt idt88k8483 figure 24 flow control m ode 1 application example flow control mode 2 - buffering in the buffering option the idt88k8483 gets the data in interleaved mode or in packet mode and it sends the data in packet mode or in interleave mode. in this option, the ebc[2:0] field in the (p. 129) should be configured to the number of fifos in the qdr-ii (64, 32, 16, 8 or 4) as described in figure 25 qdr-ii fifos allocation example for buffering option p.57 . each fifo gets the same amount of buffer size. figure 25 qdr-ii fifos allocation example for buffering option in buffering option, the pfp and the qdr-ii should be programed to packet mode by setting to 1 the pkt_mode field in the pfp egress packet mode control registers (p. 123) and the pkt_mode field in the auxiliary packet mode conf iguration register (p. 131) . in addition, the ebp_thr field in the auxiliary early backpressure threshold register (p. 131) should be programmed with the early back-pressure threshold value. also, the flow control mode 2 should be enabled in the pf p by setting to 1 the ebp_en field in the pfp egress packet mode control registers (p. 123) . the device fixes the second free segments (sec ond free segments) to 6 as shown in figure 26 qdr-ii flow cont rol example for buffering option p.58 . there are three status options per fifo in the qdr-ii: starving hungry and satisfied. in the qdr-ii for lp0 (for example), in n ormal operation there are enough free segments, so the fifo status is starving, and the qdr-ii is sending st arving status to the pfp. when the number of free segments is less than ebp_thr (for exampl e 100 segments), the qdr-ii fifo status is changed to hungry, and the qdr-ii starts sending hungry status to the pfp. when the number of free segments is less than the second free segments (6 segments), the qdr-ii fifo status is changed to satisfied, and the qdr-ii starts sending sati sfied status to the pfp. spi-4 ingress port buffer spi-4 egress port buffer pfp ingress spi-4 ingress interface spi-4 egress interface qdr pfp egress framer np 508 segments 127k bytes 508 segments 127k bytes 8k segments 2m bytes reassembly interleaved channels non-interleaved channels data status data status lid 63 lid 1 lid 0 qdr-ii (8k segments, 2m bytes, 16m bits) . . . 128 segments / 32k bytes 58 of 162 october 20, 2006 idt idt88k8483 figure 26 qdr-ii flow control example for buffering option an application example for flow control mode 2 is described in figure 22 . in this case there is no over-b ooking, and there can be frequent back- pressure. figure 27 flow control m ode 2 application example impedance matching control the auxiliary interface egress side has impedanc e matching control. it has on chip test circuit that automat ically adjusts the impedance of the auxil- iary interface egress data and control signals according to the 100 ohm pull down resistor that is connected to the qdr_imp ext ernal signal. satisfied starving satisfied qdr-ii (8k segments, 2m bytes, 16m bits) early back pressure free segments per lid 0 = 100 hungry starving second free segments per lid 0 = 6 maximum number of segments for lid 0 = 128 hungry early back pressure free segment per lid 1 = 100 second free segments for lid 1 = 6 maximum number of segments for lid 1 = 128 spi-4 ingress port buffer spi-4 egress port buffer pfp ingress spi-4 ingress interface spi-4 egress interface qdr-ii pfp egress framer np 508 segments 127k bytes 508 segments 127k bytes 8k segments 2m bytes interleaving interleaved channels non-interleaved channels data status data status 59 of 162 october 20, 2006 idt idt88k8483 generic interface overview the auxiliary interface has two modes: qdr-ii interface mode and generic interface mode. the auxiliary interface mode (qdr-ii o r generic) is configured by the mem field in the auxiliary interface configuration register (p. 129) . the auxiliary interface has to be configured before the interface is enabled. the auxiliary interface outputs (except for the clock) can be powered down by setting to 1 the aux_pdn field in the auxiliary interface enable register (p. 129) . the interface is enabled by setting to 1 the aux_en field in the auxiliary interface enable register (p. 129) . the generic interface can be connected to an fpga. the interface has 32 bits ingress data bus, 4 bits ingress control bus, 32 b its egress data bus and 4 bits egress control bus. the 4 bits control bus carries t he control information that indicates the transfer type, and the 32 bits data bus curries the transfer data. the interface has also differential clk ingress clock and differential clk egress clock. the ingress flow control mess ages are transmitted on the egress channel. the egres s flow control messages are transmitted on th e ingress channel. the flow control mechanism prov ides both per link level flow contro l and interface level flow control. the g_vref signal should be conn ected to 0.75v generated from the vddh15 power suppl y using regulator or pot-divider like max15 10 as shown in figure 42 idt88k8483 vdda25 filter circuit p.75 . figure 28 idt88k8483 and fpga connections transfer format for normal data the generic interface format is defined to map 1-256 bytes payl oad in a proprietary transfer form at. the transfer format for no rmal data is shown in figure 29 (dm is dummy information) . the minimum payload transfer length is 2 words (1 word is 1 data cycle). the first word of a transfer carries the lid information. lid[5:0] is mapped into b[5:0] of the first byte. the control field of the first transfer is sop o r sot. figure 29 generic interface - transfer format for normal data fpga g_edat[31:0] g_ectl[3:0] g_idat[31:0] edat[31:0]] g_eclkp ectl[3:0] ictl[3:0] g_ictl[3:0] idat[31:0] eclkp g_eclkn eclkn iclkp iclkn g_iclkp g_iclkn idt88k8483 g_vref g_imp v ddh15 /2 100 ohm ctrl[0] dm dat[0] lid dm dm dm dm dm dm b0/dm b0 b3/dummy b2/dm b5/dm d4/dm b7/dm b6/dm ctrl[1] ctrl[0] ctrl[1] dat[31] ctl[0] ctl[3] 60 of 162 october 20, 2006 idt idt88k8483 the lid field in the transfer format for normal data includes the lid number (lid0,lid2,lid3,...). the control field is encoded to indicate the type of data word as described in ta b l e 4 . transfer format for status word the transfer format for status word is shown in figure 30 . the lid information is the pfp back-pressure status (starving, hungry, or satisfied). figure 30 generic interface - transfer format for stratus word. ctrl[1], ctrl[0] description 00000000 eop 1b without error tag 00000001 eop 2b without error tag 00000010 eop 3b without error tag 00000011 eop 4b without error tag 00000100 eop 5b with error tag 00000101 eop 6b without error tag 00000110 eop 7b without error tag 00000111 eop 8b without error tag 00001000 eop 1b with error tag 00001001 eop 2b with error tag 00001010 eop 3b with error tag 00001011 eop 4b with error tag 00001100 eop 5b with error tag 00001101 eop 6b with error tag 00001110 eop 7b with error tag 00001111 eop 8b with error tag 00010000 sop 00010001 sot 00010010 eot 00010011 normal data, mated receive side ready 00010100 normal data, mated receive side full 00010101 status word, mated receive side ready 00010110 status word, mated receive side full 00010111~11111111 reserved table 4 generic interface - control field coding ctrl[0] lid1 dat[0] lid0 lid31 ..... lid33 lid32 lid63 ...... ctrl[1] dat[31] ctl[0] ctl[3] 61 of 162 october 20, 2006 idt idt88k8483 interface operation the egress channel generates the trans fer format and the local status information. the ingress channel detects the transfer for mat and status information from the adjacent device. each word of the ingress interface is cl assified by decoding the control field. the reserved control field is ignored. the devi ce extracts the lid from the first word of a transfer, and the following payload belongs to this lid. the egress channel generates the transfer form at. the data is transferred to the interfac e, and the link level status word can interrupt the transfer. flow control the fpga has link level back-pressure and in terface level back pressure. the interface level back-pressure information is carri ed on the control signal (ictl[3:0] and ectl[3:0]). the link level flow c ontrol is using the transfer format status word. impedance matching control the auxiliary interface egress side has impedanc e matching control. it has on chip test circuit that automat ically adjusts the impedance of the auxil- iary interface egress data and control signals according to the 100 ohm pull down resistor that is connected to the g_imp exter nal signal. 62 of 162 october 20, 2006 idt idt88k8483 microprocessor interface overview the microprocessor interface can be in serial mode or in parallel mode. when the exter nal signal spien is cleared to 0, the int erface is in parallel mode, and when spien signal is set to 1, the interface is in serial mode. the parallel microprocessor interface c an be connected directly to a suitable pr ocessor or to a fpga as shown in figure 31 microprocessor interface - parallel mode p.62 . the interface has 8 bits data bus and 6 bits address bus. the interface has also write, read, chip select and inter- rupt signals. in addition there is a mode signal : mpm. when mpm signal is set to 1, the interface is in intel mode, and when mp m signal is cleared to 0, the interface is in motorola mode. . figure 31 microprocessor interface - parallel mode the serial microprocessor interface can be c onnected directly to a suitable processor or to a fpga. the interface has data, chi p select and clock signals.the microprocessor interface timing is based on the main cl ock domain. one microprocessor interface cycle is four main clock cycles. embedded processor download the embedded processor has 2 mailboxes, i_fifo and o_fifo each of wh ich has a 32 byte fifo. mailbox i_fifo is used for firmware download from the host to the embedded processor. refer to page 90 and page 92 for registers related to the mailbox fifos. the embedded processor is first checked to see if it is ready for download. this is done by reading direct register 0x16. if t he result is 0x1, then further downloading steps take place as indicated in the flowchart below. the download should take place in the little endian format. if the download file is in big endian format and since the downloa ding takes place in 16 bit words, the lower byte should be swapped with the upper byte. idt88k8483 processor / fpga dat[7:0] adr[5:0] wrb csb rdb intb spien mpm dat[7:0] add[5:0] wrb csb rdb intb vdd 63 of 162 october 20, 2006 idt idt88k8483 firmware download flowchart example for download sequence an example pseudo code of how the downl oad sequence is implemented is shown below download { write rst=0x1 // rst field is in global software reset register (p. 90) read ep_state // field is in embedded processor state register (p. 92) if(ep_state == 1) { while( !eof) { // read binary data until end of file is encountered while(ififo_status != 0) && (time < wait_time)) { // field is in microprocessor mailbox input fi fo status register (p. 91) if(time == wait_time) return ?wait time error? else { write i_fifo = 32 bytes binary data or less than 32 if eof is encountered // i_fifo is in microprocessor mailbox input fifo data register (p. 90) write length = binary data length written to i_fifo // length field is in microprocessor mailbox input fifo length register (p. 90) // writing to the length register causes the embedded processor to dow nload from the i_fifo mailbox. } } // end of while status loop } // end of while !eof loop } // end of if ep_state loop start readreg 0x16 ( ep_ready ) result readreg 0x14 ( ififo_status ) result writereg 0x10 ( data ) is 32 bytes written? or eof reached writereg 0x11 ( length ) is eof reached 0 1 1 0 yes no yes no start (download is not successful) result readreg 0x16 0x7 end !=0x7 (download is successful) 1 64 of 162 october 20, 2006 idt idt88k8483 } // end of download interrupt the device captures events in the primary interrupt indication register (p. 98) . the interrupt status fields in the primary interrupt indication register (p. 98) are cleared by writing 1 to the appropriate field. the device has two interrupt levels: a primary level and a secondar y level. the primary level stat us indicates the interrupt st atus of module a/b/ common. the secondary level status indi cates the interrupt status per module. figure 32 interrupt scheme event enable interrupt status enable & | | intb interrupt status module status primary interrupt level secundary interrupt level & captured event 65 of 162 october 20, 2006 idt idt88k8483 pmon pmon events there are few event types: field associated non-critical event, field associated cr itical event, non field associated events. t he events are described in the tables below. when a field associated non-critical event is captured, the lid or lp (which is a ssociated the event) is captured, and the tabl e register records the latest captured lid or lp. for field associated critical event, only one kind of critical event is defined, and it is per lid captured. tm_ovf field in th e pmon buffer overflow source register (p. 142) indicates the or result of 64 lids status of t_m direction. mt_ovf field in the pmon buffer overflow source register (p. 142) indicates the or result of 64 lids status of m_t direction. non field associated events are capt ured without any associated field. table 5 field associated non-critical event list table 6 field associated critical event list event name associated field definition main ingress inactive lp lp this event is raised when an inactive logical port is encountered. t-m illegal sop lid please refer to page 52 for an explanation for when this event is raised. t-m illegal eop lid please refer to page 52 for an explanation of when this event is raised. m-t illegal sop lid please refer to page 52 for an explanation of when this event is raised. m-t illegal eop lid please refer to page 52 for an explanation of when this event is raised. t-m packet cut down lid please refer to page 52 for an explanation of when this event is raised. m-t packet cut down lid please refer to page 52 for an explanation of when this event is raised. event name associated field definition t-m buffer overflow lp global buffer overflow or per link overflow. m-t buffer overflow (lid0-63) lid global buffer overflow or per link overflow. 66 of 162 october 20, 2006 idt idt88k8483 table 7 non field associated event list counters there are two types of counters: per lid counters and per module counters. the per lid counters are described in the pmon per lid counter table (p. 144) . the per module counters are described in the pmon per module/interface counter table (p. 144) . event name remark definition tributary spi4 ingress locker unavailable tributary spi4 ingress locker unavailable main spi4 ingress locker unavailable spi4 interface tributary ingress data clock loss spi4 interface tributary egress status clock loss spi4 interface main ingress data clock loss valid for module a spi4 interface main egress status clock loss valid for module a spi4 interface tributary spi4 dip-2 spi4 interface tributary spi4 dip-4 spi4 interface tributary spi4 bus error please refer to page 44 for an explanation of bus error. tributary ingress synch status change spi4 interface tributary egress synch status change tributary egress synch status change. main spi4 dip-2 valid for module a spi4 interface main spi4 dip-4 valid for module a spi4 interface main spi4 bus error valid for module a spi4 interface main ingress synch status change valid for module a spi4 interface main egress synch status change valid for module a 67 of 162 october 20, 2006 idt idt88k8483 figure 33 pmon measure points aux insert ingress locker loop prbs extract egress locker redirect spi4 a spi4 m obc insert ingress locker loop obc extract egress locker redirect spi4 a + + + + aux extract egress locker loop prbs insert ingress locker redirect spi4 b spi4 m obc extract egress locker loop obc insert ingress locker redirect spi4 a + + + + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 68 of 162 october 20, 2006 idt idt88k8483 time base a single pmon time base is provided for t he device. the time base can be generated inter nally or externally according to the in ternal field in pmon 1ms timer register (p. 145) . the internal time base can be generated by a free running timer or obc according to the timer field in the pmon 1ms timer register (p. 145) . the time base sources are described in the ta bl e 8 . table 8 time base source internal pmon time base the device has a 1ms accurate timer. the 1m s timer register specifies t he number of mclk for generati ng 1ms time intervals. a 1 0ms event is generated based on the 1ms timer, and forwarded to the in terrupt module and to the internal embedded processor. in internal timer mode, the device generates one time base trigger in each second. in internal obc mode, writing 1 to the manua l field in the pmon 1ms timer register (p. 145) generates a time base trigger. the one se cond is generated based on the 1ms timer. the time base trigger generates a 16-mclk high pulse to timebase pin, and it updates t he pmon counters. the time base trigger a lso gener- ates a timebase interrupt event to the interrupt module. the del ay between the time base trigger and the timebase interrupt eve nt is 3 to 4ms. subsequent trigger is ignored during the this period. the internal pmon ti me base wave form is shown in figure 34. figure 34 internal pmon time base external pmon time base a positive edge on the timebase pin generates an externally time bas e trigger. the time base trigger updates the pmon counters, and gener- ates a timebase interrupt to the interrupt module. the delay between the time base tr igger and the timebase event is 3 to 4 ms. subsequent trigger is ignored during this per iod. the external pmon time base wave form is shown in figure 35. [internal, timer, manual ] time base trigger source 3?b0xx the time base is generated externally. 3?b11x the internal time base is generated by a free running timer. 3?b10x the internal time base is generated by obc. timebase trigger timebase interrupt signal to timebase pin 3-4ms for pmon updating 16 mclk cycles 69 of 162 october 20, 2006 idt idt88k8483 figure 35 external pmon time base clock idt88k8483 has three programmable clock gener ators (main, tributary a and tributary b) . one clock generator (main) is type m an d two clock generators (tributary a and tributary b) are type t. there are three input clocks sp i4a_rclk, spi4b_rclk and spi4m_rclk. each o ne of the clock inputs is a clock source to one of the th ree internal clock generators. the device al so has 4 clock confi guration signals (div4 , spi4a_clk_sel, spi4b_clk_sel, and spi4m_clk_sel) for programing the clock generator s. the clock generator type m includes the following blocks : prescaler, pll and three independent dividers as described in figure 36 clock generator type m p.70 . the clock generators type t include the following blocks: prescaler, pll and two independent dividers as described in figure 37 clock generator type t p.70 . the external configuration signals spi4a_clk _sel, spi4b_clk_sel and spi4m_clk_sel configure the divider 1 frequency to divide b y 2 or 8 as described in ta b l e 9 . the external signals spi4a_clk_sel, spi4b_clk_sel and spi4m_clk_sel value are reflected by ck_sel_a, ck_sel_b and ck_sel_c fields in the clock control input status register (p. 104) . the external configuration signal div4 configures the prescaler frequency to divide by 4 or 1 as described in table 10 . the external signal div4 value is reflected by div_four field in the clock control input status register (p. 104) . cksel (external input signal: spi4a_clk_sel, spi4b_clk_sel, spi4m_clk_sel) edclk / isclk_t (external output signals) operation mode 0 plloclk / 2 (plloclk is internal signal) full rate 1 plloclk / 8 (plloclk is internal signal) quarter rate table 9 clk_sel signals configuration div4 (external input signal) pllrclk (internal signal) operation mode 0 rclk / 1 (rclk is external input signal: spi4a_rclk, spi4b_rclk, spi4m_rclk) full rate 1 rclk / 4 (rclk is external input signal: spi4a_rclk, spi4b_rclk, spi4m_rclk) quarter rate table 10 div4 signal configuration timebase trigger timebase interrupt 3-4ms for pmon updating 70 of 162 october 20, 2006 idt idt88k8483 clock generator type m clock generator type m generates the internal clock mclk and the external spi-4 main interface clocks (edclk, isclk, isclk_t) a s shown in figure 36 clock generator type m p.70 . the mclk clock is used for the generic interfac e, the pfp block and the pmon block. the clock generator source is the external si gnal spi4m_rclk. the mclk frequency is selected by the n field in the mclk divider sticky register (p. 104) . the n field value can be modified at any ti me during normal operation. the spi-4 operati on rate is selected by the external sig nal spi4m_clk_sel. the external signal div4 configures the prescaler frequency to divide by 4 or 1. figure 36 clock generator type m clock generator type t clock generator type t generates the spi -4 tributary interface clocks (edclk, isclk, isclk_t) as shown in figure 37 clock generator type t p.70 . the clock generator sources are the exter nal signals spi4a_rclk and spi4b_rclk. spi-4 operation rate is selected by the exter nal signals spi4a_clk_sel and spi4b_clk_sel. the external signal di v4 configures the prescaler frequency to divide by 4 or 1. figure 37 clock generator type t * 32 pll isclk edclk spi4m_rclk div 2/8 div 4 mclk isclk_t spi4m_clk_sel div 4/1 div 2/3/4/5 prescaler div4 n * 32 pll isclk edclk spi4a_rclk spi4b_rclk div 2/8 div 4 isclk_t spi4a_clk_sel spi4b_clk_sel div 4/1 prescaler div4 71 of 162 october 20, 2006 idt idt88k8483 design consideration system reset there are two methods for resetting the id t88k8483: hardware reset and software reset. du ring reset the output clocks are not t oggled. hardware reset the resetb input requires an active low pulse to reset the internal logic. software reset the software reset is triggered by setting to 1 the rst field in global software reset register (p. 90) . the response to a software reset is identical to a hardware rest except that softwar e reset does not change the n field in the mclk divider sticky register (p. 104) , so it does not impact the clock generators. after software reset the mi croprocessor should have delay of at least 2ms before accessing the device. power on sequence figure 38 power-on-reset sequence a correct power-on-reset sequence is crucial for the normal behavior of the devic e. the power-on-reset sequence includes the fo llowing signals: rclk (spi4a_rclk, spi4b_rclk, spi4m_rclk), vdd (vdd33, vdd l25, vddh25, vddh15, vddl12, vd dc12, vtt) and resetb (resetb). figure 38 power-on-reset sequence p.71 illustrates the recommended implementation for t he power-on-reset sequence for the device. idt recommends powering up the 3.3v (vdd33) power supply first, the 2. 5v (vddl25, vddh25) power supply second, the 1.5v (vddh15) po wer supply third, the 1.2v (vddc12, vddl12) power supply fourth, and the 0.75v (vtt) power supply last. the power supplies can be also pow ered up in the same time. there is no requirement for t he minimum or maximum delay between the power -up of the power supplies. the power suppl ies should be powered off in the reverse order. the pow er ramp should not be faster than 100us. when the power supplies are powered up, the resetb signal should be at low level. duri ng power-on-reset, after the vdd, rclk an d the config- uration signals are stable, the resetb signal should remain at a low level at least 10ms (symbol ?t1?) to reset the internal lo gic. after the resetb pulse ends, the device starts generating the spi-4 ex ternal output clocks and the mclk internal clock. t1 rclk vdd33 resetb t3 t2 vddc12 . . . 72 of 162 october 20, 2006 idt idt88k8483 after the resetb pulse ends, a delay of 2ms should be added (symbol s ?t2? and ?t3?) before accessing the device for initializat ion and configu- ration. this allows the internal logic to be stable. during t2 (at least 1ms delay) the device perf orms internal memories initi alization, and during t3 (at least 1ms delay) the device run a boot code from the internal embedded processor rom. after t3, the user should poll the chip_ready field in the embedded processor state register (p. 92) , and wait until it is 1. when the chip_ready field is 1, the user should dow nload the firmware binary file from the ex ternal microprocessor to the idt88k8483 emb edded processor ram. jtag ieee boundary scan standard 1149.1, informally known as jtag (joi nt test action group), is a testing standard that uses softwar e to reduce testing costs by eliminating the need for a sophisticated in-cir cuit test equipment. the inclusion of boundary-scan registers i n integrated circuits greatly improves the testability of boards. boundary scan provides a mec hanism for testing component input, output and inter-connection s. devices containing boundary scan have the capability of driving or observing the logic levels on i/o pins by utilizing the tap (test ac cess port). the tap controller, a 16-state moore-type state machi ne, dictates the control of all jtag acti vities through four pins: tdi (test data input), tdo (test data output), tms (test mode select), and tck (test clock). data is passed serially from one device to the next, thus forming a boundary-scan path or chain from tdi (test data input) that originates at the test controller and returns there, through the scan path, to tdo. to test the external interc onnect, devices drive values at th eir outputs and observe input values received from other devices. an external test controller compares t he received data with expected results. any dev ice can be temporarily removed from the boundary-scan path by bypassing its internal shift registers, and passing the serial data directly onto the ne xt device. this allows efficient testing of a selected device without incurring the ov erhead of traversing through other devices. jtag testing can als o be used to check the inter connectivity of external memory devices by generating read and write test ve ctors independent of the chip functionality. the read and write vector results can then be read back to ensure that the memory devices are connected correctly. design for test idt strongly recommends that its customers use jtag testing fo r both prototypes and production boards. large pin count devices, and in partic- ular ball grid arrays require c onfidence in the correct assembly of the init ial prototype boards. the idt88k8483 chip has 672 p ins fcbga. bed-of- nails testing does not allow the testing of bga mounting to the boar d. jtag testing is very effective at isolating assembly err ors down to individual signals in a very short time. during the board bring-up process, several weeks have been spent identifying problems that turned out to be incorrectly assembl ed boards, partic- ularly bgas not mounted correctly to the boar d. using jtag enables the issues to be i mmediately identified if design for test i s considered from the outset. it is possible for the customer to generate comprehensive jt ag tests within a week of becoming familiar with the approp riate equipment and tools. the time between gerber files goi ng to fabrication and the board?s return can be used to generate the appropriate jtag t ests, thus limiting schedule impact. the effort is also much less than that requir ed to develop functional diagnostic tests to exercise and test ev ery individual pin. jtag results in considerable time saving during the prototype bring-up, which can be one of the most significant causes of delays in overall time-to-market. idt's bring-up strategy is based on the assumption that the cu stomer?s board is correctly assembled, and has been tested to ens ure proper assembly before attempting to run any functional tests. idt88k8483 jtag testing the idt88k8483 supports board-level testing thr ough the use of a jtag test port. the test port comprises the following pins: jt di (test data input), tdo (test data output), tms (test mode select), tck (t est clock), and trstb (test rese t). the tck clo ck frequency is up to 10mhz. when jtag testing is used on the board, all the devices should be jtag daisy-chained, tdo to tdi as shown in figure 39 jtag daisy chain p.73 . note that the pins on the jtag connector are named so that td i drives the tdi of the first device and tdo is driven by tdo of the last device. also, the tck, tms and trstb signal s of all the devices should be connected t ogether and driven from the jtag connector . 73 of 162 october 20, 2006 idt idt88k8483 the internal jtag logic of each device powers up in an unknown state, so it is necessary at power-on to reset it to the test-lo gic-reset state so that the chip operates properly. this can be done in one of the three different ways: 1. trstb is pulled low by a resistor. trstb must also connect to the jtag connector, and the jtag tester must drive trstb high for jtag testing. 2. a low pulse is applied to trstb at power on as shown in figure 40 trstb signal during power-on reset p.73 . note that a falling edge is not required on trstb. trstb can then be held high as long as tms is also pull ed high, thereby keeping the logic in the reset state. this method is appropriate if the jtag tester does not drive trstb. 3. tck can be clocked five or more times while tms is held high. in this case, trstb can be pull ed high. this method is also ap propriate if the jtag tester does not have trstb. figure 39 jtag daisy chain the trstb signal is an option reset pin and may not be available on all jtag test c onnectors. trstb should be held high during jtag testing. once in the test-logic-reset test, the jtag logic will remain in this state as long as tms is high, regardless of the state of trstb. figure 40 trstb signal during power-on reset the tck signal should be carefully routed on board according to standard layout design to minimi ze skew and noise problems. jtag specifications require that pull-up re sistors be supplied internally to the tdi, tr stb, and tms pins in the chips. very lo ng jtag chains or parts from different vendors may present si gnificant loading to the controller. to co mpensate for this, the designer should inc lude buffers on tms, trstb and tck to account for unknown device impedance. for syste ms with several components, the designer should use a high fan- out buffer. tdi jtag connector tck tms trstb tdo tdi idt88k8483 - 1 tck tms trstb jtdo tdi idt88k8483 - 2 tck tms trstb tdo tck tms trstb tck tms trstb vdd vdd tck tms trstb 74 of 162 october 20, 2006 idt idt88k8483 ensure that the buffer has sufficient drive capability to supply all loads. when using a buffer to drive any of the jtag tap pi ns, it may be necessary to include an external resistor to ensure the pin is set to the correct state when the buffer is idle. thus, trstb should have an external resistor to ground when driven by an external buffer and tms and tck should each have an external pull-up. the jtag instructions are described in table 11 . the jtag id information is described in table 12 . gpio the device has 3 general purpose input/out put pins. the pins? direction is independently controlled by the di r_out field in the gpio direction register (p. 145) . the logical level on the pins is c ontrolled by the level field in the gpio level register (p. 146) . the level field reflects the status of any bit which is selected from the indirect access space if enabled. a bit in the indirect access space can be selected by t he address and bit fields in the gpio link table (p. 146) . a bit can be enabled by the reflect_en field in the gpio link table (p. 146) . idt recommends to connect all the unused gpio signals to an fpga or microprocessor pins for debugging purpose. power supply the idt88k8483 power supplies can be generated as shown in the design example in figure 41 idt88k8483 power supply genera- tion example p.75. the idt88k8483 system should have the following: 1. connect the v dda25 signals through filter to the v ddh25 / v ddl25 signals as described in figure 42 idt88k8483 vdda25 filter circuit p.75 . 2. connected together the v ddh25 signals and the v ddl25 signals. 3. separate the v ddc12 signals and v ddl12 signals. 4. generate the v ddl25 / v ddh25 signals from v ddt33 signals. 5. generate the v tt075 signals from v ddh15 signals. instructions instruction codes function description extest 000 test the function to other devices idcode 001 used to connect the identification register highz 100 set outputs to hi-z state clamp 011 clamp the output latches sample 010 sample all the inputs and outputs runbist 110 bist usercode 101 user code bypass 111 used to bypass the device table 11 jtag instruction code version part number manufacture id fixed 0 0x4af 0x33 1 table 12 jtag id 75 of 162 october 20, 2006 idt idt88k8483 6. connect the v spi4a_vref , v spi4b_vref and v spi4m_vref signals through filter to vd dl12 signals as described in figure 43 idt88k8483 spi4x_vref filter circuit p.75 . 7. generate the v qdr_vref /v g_vref signals from the v ddh15 power supply using regulator or pot-divider like max1510 ( v ddh15 /2). figure 41 idt88k8483 powe r supply generation example figure 42 idt88k8483 vdda25 filter circuit figure 43 idt88k8483 spi4x_vref filter circuit 0.75refout max1510 refin v ddh15 /2 v ddt33 10k v ddh15 10k 1nf vcc agnd pgood 100k v ddt33 10uf in v ddt33 out 75v outs 1nf v ddt33 shdn pgnd 10uf vout power convertor gnd v ddc12 470uf 3.9k vin 12v 47uf 470uf trim rmt_on_off power_on signal from cpld vout power convertor gnd v ddh15 470uf 3.9k vin 12v 47uf 470uf trim rmt_on_off power_on signal from cpld power_on signal from cpld vout dc-dc convertor gnd v ddt33 470uf 3.9k vin 12v 47uf 470uf trim rmt_on_off 2.5vout mic37300-2.5 gnd v ddt33 470uf vin 47uf tab v ddt33 sil06c-33sadj-v (artesyn) sil06c-15sadj-v (artesyn) sil06c-12sadj-v (artesyn) v dda25 1uf 1uf 4.7uf v ddh25 /v ddl25 ferrite bead v ddl12 1uf 1uf 4.7uf v spi4a_vref /v spi4b_vre /v spi4c_vref ferrite bead 76 of 162 october 20, 2006 idt idt88k8483 configuration sequence before writing the configuration flow, design and determine the device c onfiguration including: ? specific application ? data path ? mapping relation between link and logic port ? working mode of each link the device configuratio n flow is as follows: 1. download the firmware binary file to the embedded processor and check if the chip has been initialized to a state that user can access it. 2. configure the pmon timebase, if you want to use the internal timer. 3. configure the pfp including the followi ng parameters: link id number, buffer size, cut through/packet mode, backpressure thr eshold, burst size, weight and direction, etc. 4. configure the spi4 interface, including ingress/egress logical port mapping, calendar configuration, interface initializatio n and enabling, and synchronization check. 5. initialize auxiliary interface memory/gener ic mode, if you use auxiliary interface. 6. initialize prbs module, if you use prbs insert/extract. 7. during the traffic test check the device status by reading various information, such as pmon statistic information, pfp/spi4 status information and interrupt information. note: please refer to the programming guide for device configuration examples. 77 of 162 october 20, 2006 idt idt88k8483 registers register organization: there are two types of register in the idt88k8483: direct registers: direct registers are used for high-priority registers such as interrupts and for access to the indirect registers. direct regis ters can be accessed more quickly than indirect registers. all direct access registers ar e one byte wide. direct registers used for accessing indirect registers are known as indirect access r egisters.they consist of 8 bit address regist ers, data registers and control registers. the direct registers address space, size and type is shown in table 13. indirect registers: indirect access registers are used for co nfiguration, maps, etc. they are accessed via the direct register space by means of a protocol which maps microp rocessor interface pins a[5:0] d[7:0] and control pins to internal register space a[19:0], d[31: 0], and control[7:0]. the indirect register address s pace and register size is shown in table 14. register access protocol. direct access the direct access registers have 8 bit dat a (one byte data) and 8 bits address as s hown in table 13.these are accessed via the microprocessor interface. read operations to a reserved address or reserved bit fields return 0. write operations to reserved addr ess or bit fields are discarded. indirect access the indirect access scheme uses the indire ct access address register, indirect access control register and indirect access data register to map a 24 bit indirect address, and 32 bit data into the indirect regist er. the control register validat es the access request and perform s operations accordingly. the direct registers used for indire ct access are shown in table 15. figure 44 indirect register access scheme register address size (bits) register address range (hex) register data size (bits) type 8 i 0x0 to 0x25 8 i read/write, read only, write only. table 13 direct register table register address size (bits) re gister data size (bits) type 20 i 8 i or 32 i read/write, read only, write only. table 14 indirect register table processor interface direct accessed space indirect accessed space a d c a d c 8 6 20(16) 32 78 of 162 october 20, 2006 idt idt88k8483 the indirect register accessing scheme: 3 byte indirect register address = 3 byte segment base address + 2 byte module base address + 2 byte block base address + 1 byte register offset direct register address (hex) register size (bits) used for type 0x1a 8 indirect access control read/write 0x1b 8 indirect access data (byte 0) read/write 0x1c 8 indirect access data (byte 1) read/write 0x1d 8 indirect access data (byte 2) read/write 0x1e 8 indirect access data (byte 3) read/write 0x1f 8 indirect access address (byte 0) read/write 0x20 8 indirect access address (byte 1) read/write 0x21 8 indirect access address (byte 2) read/write address name no of bytes description segment base 3 address based on user registers or idt reserved registers. module base 2 address based on module a, b or common module which includes the spi4 interfaces, pfps and associated pmons, insert, extract registers. block base 2 address based on blocks of registers related to spi4 ingress and egress interfaces, related pfps and pmons, auxillary interface, processor interface. register offset 1 address of the individual registers for each block base. 79 of 162 october 20, 2006 idt idt88k8483 indirect read and write operation: i ndirect write access operation ? the obc reads the busy flag in the microprocessor indirect acce ss control register (p. 93). it proceeds only when the flag is cl eared. ? the indirect write access operation is tr iggered by a write operation in the indirect access control register. this is achieved by setting field rwn to 0 in the microprocessor indire ct access control register (p. 93). ? the process sets the busy flag in the i ndirect access control regi ster immediately and verifi es the indirect address. ? when the address is out of bounds, no internal memo ry is accessed and the busy flag is cleared. ? when the address is within bounds the indirect wr ite operation is achiev ed as soon as possible. ? the busy flag is cleared as soon as the write operat ion is completed and the address is auto incriminated ? the error field in the microprocessor indirect access cont rol register (p. 93) indicate s an errorcode.correct operation returns error = 0 . figure 45 indirect access module indirect read access operation ? the indirect read access operation is tri ggered by a read operation to the indirect ac cess control register. this is achieved b y setting field rwn to 1 in the microprocessor indire ct access control register (p. 93). ? the process sets the busy flag in the i ndirect access control regi ster immediately and verifi es the indirect address. ? when the address is out of bounds, no internal memory is accessed and the busy flag is cleared. also the indirect access data r egis- ters(p.85) are cleared. ? when the address is within bounds the indirect read operation is achieved as soon as possible. ? the busy flag is cleared as soon as the read operation is completed and the address is automatically incremented. ? the error field in the microprocessor indire ct access control register (p. 93) indica tes an error code. correct operations retur n error = 0. address data control indirect access process address data control direct access indirect access data bond[1:0] 80 of 162 october 20, 2006 idt idt88k8483 register map direct registers map register offset register name 0x 0 pfp t-m insert control register for module a (p. 96) 0x 1 pfp t-m insert data register for module a (p. 97) 0x 2 pfp t-m extract control register for module a (p. 97) 0x 3 pfp t-m extract data register for module a (p. 97) 0x 4 pfp m-t insert control register for module a (p. 97) 0x 5 pfp m-t insert data register for module a (p. 97) 0x 6 pfp m-t extract control register for module a (p. 98) 0x 7 pfp m-t extract data register for module a (p. 98) 0x 8 primary interrupt indication register (p. 98) 0x 9 primary interrupt enable register (p. 99) 0x a secondary interrupt module a indication register (p. 100) 0x b secondary interrupt module a enable register (p. 100) . 0x c secondary interrupt module b indication register (p. 101) 0x d secondary interrupt module b enable register (p. 101) 0x e secondary interrupt common indication register (p. 102) 0x f secondary interrupt common enable register (p. 103) 0x 10 microprocessor mailbox input fifo data register (p. 90) 0x 11 microprocessor mailbox input fifo length register (p. 90) 0x 12 microprocessor mailbox output fifo data register (p. 91) 0x 13 microprocessor mailbox output fifo length register (p. 92) 0x 14 microprocessor mailbox input fifo status register (p. 91) 0x 15 microprocessor mailbox output fifo status register (p. 92) 0x 16 embedded processor state register (p. 92) 0x 17 reserved 0x 18 reserved 0x 19 reserved 0x1a microprocessor indirect access control register (p. 93) 0x 1b microprocessor indirect access data register - 1 (p. 93) 0x 1c microprocessor indirect access data register - 2 (p. 94) 0x 1d microprocessor indirect access data register - 3 (p. 94) 0x 1e microprocessor indirect access data register - 4 (p. 95) 0x 1f microprocessor indirect access address register - 1 (p. 95) 0x 20 microprocessor indirect access address register - 2 (p. 95) table 15 direct registers map (part 1 of 2) 81 of 162 october 20, 2006 idt idt88k8483 indirect registers map indirect register addressing = segm ent base address + module base address + block base address + register_offset segment base address there are five segments defined for indirect registers as shown in table 16 .. only the user_seg is used by the users. module base address there are three modules defined for indirect registers as shown in table 17 . 0x 21 microprocessor indirect access address register - 3 (p. 95) 0x 22 global software reset register (p. 90) 0x 23 reserved. 0x 24 reserved. 0x 25 reserved. segment base address segment base name segment base description 0x00000 user_seg user register 0x10000 reserved registers reserved for use by idt 0x20000 reserved registers reserved for use by idt 0x30000 reserved registers reserved for use by idt 0x40000 reserved registers reserved for use by idt table 16 indirect registers map - segment base address module base address module base name module base description function 0x0000 module_a tributary spi-4 a, pfp a and associated pmon, insert/extract registers spi-4, pfp, pmon 0x2000 module_b tributary spi-4 b, pfp b and associated pmon, insert/extract registers spi-4, pfp, pmon 0x8000 common main spi-4, clock generator, gpio and chip version registers spi-4, pfp, pmon table 17 indirect registers map - module base address register offset register name table 15 direct registers map (part 2 of 2) 82 of 162 october 20, 2006 idt idt88k8483 block base address and register offset there are block bases defined for module registers ( tributary spi-4 a, pfp a and associated pmon, insert/extract and tributary spi-4 b, pfp b and asso- ciated pmon, insert/extract ) and for common ( main spi-4, clock generator, gpio and chip version ) as shown in table 18 . indirect registers map module base address block base name block base address register offset indirect register address 0x register description m:0x8000 clk_gen 0x0a00 0x00 m: 08a00 mclk divider sticky register (p. 104) m:0x8000 clk_gen 0x0a00 0x01 m: 08a01 clock control input status register (p. 104) a:0x0000 b:0x2000 m:0x8000 lp2lid_map 0x0000 0x00-0xff a: 00000 - 000ff b: 02000 - 020ff m:08000 - 080ff spi-4 ingress lp to lid mapping table (p. 105) a:0x0000 b:0x2000 m:0x8000 ingress_cal0 0x0100 0x00 -0xff a: 00100 - 0013f b: 02100 - 0213f m:08100 - 0817f spi-4 ingress calendar 0 table (p. 105) a:0x0000 b:0x2000 m:0x8000 ingress_cal1 0x0200 0x00 -0xff a: 00200 - 0023f b: 02200 - 0223f m:08200 - 0827f spi-4 ingress calendar 1 table (p. 105) spi-4 ingress register group a:0x0000 b:0x2000 m:0x8000 ingress_reg 0x0300 0x00 a: 00300 b: 02300 m:08300 spi-4 interface enable register (p. 106) a:0x0000 b:0x2000 m:0x8000 ingress_reg 0x0300 0x01 a: 00301 b: 02301 m:08301 spi-4 ingress configuration register (p. 106) a:0x0000 b:0x2000 m:0x8000 ingress_reg 0x0300 0x02 a: 00302 b: 02302 m:08302 spi-4 ingress training parameter register (p. 107) a:0x0000 b:0x2000 m:0x8000 ingress_reg 0x0300 0x03 a: 00303 b: 02303 m:08303 spi-4 ingress calendar 0 configuration register. (p. 107) a:0x0000 b:0x2000 m:0x8000 ingress_reg 0x0300 0x04 a: 00304 b: 02304 m:08304 spi-4 ingress calendar 1 configuration register (p. 108) a:0x0000 b:0x2000 m:0x8000 ingress_reg 0x0300 0x05 a: 00305 b: 02305 m:08305 spi-4 ingress status register (p. 108) a:0x0000 b:0x2000 m:0x8000 ingress_reg 0x0300 0x06 a: 00306 b: 02306 m:08306 spi-4 ingress diagnostics register (p. 109) a:0x0000 b:0x2000 m:0x8000 ingress_reg 0x0300 0x07 a: 00307 b: 02307 m:08307 spi-4 ingress automatic alignment control register (p. 109) table 18 indirect registers map (part 1 of 8) 83 of 162 october 20, 2006 idt idt88k8483 a:0x0000 b:0x2000 m:0x8000 ingress_reg 0x0300 0x08 a: 00308 b: 02308 m:08308 spi4 ingress calendar switch control register (p. 109) a:0x0000 b:0x2000 m:0x8000 ingress_reg 0x0300 0x 0b-0x0c a: 0030b b: 0230b m: 0830b - 0830c spi-4 ingress fill level register (p. 110) a:0x0000 b:0x2000 m:0x8000 ingress_reg 0x0300 0x 0d-0x0e a: 0030d b: 0230d m:0830d - 0830e spi-4 ingress max fill level register (p. 110) a:0x0000 b:0x2000 m:0x8000 ingress_reg 0x0300 0x 0f-0x10 a: 0030f b: 0230f m:0830f - 08310 spi-4 ingress watermark register (p. 111) a:0x0000 b:0x2000 m:0x8000 ingress_reg 0x0300 0x13 a: 00313 b: 02313 m:08313 spi-4 ingress training to out of sync threshold register (p. 111) a:0x0000 b:0x2000 m:0x8000 ingress_reg 0x0300 0x14 a: 00314 b: 02314 m:08314 reserved a:0x0000 b:0x2000 m:0x8000 ingress_reg 0x0300 0x15-0 x24 reserved reserved a:0x0000 b:0x2000 m:0x8000 lid2lp_map 0x0400 0x00-0x7f or 0x00- 0x3f a: 00400- 0043f b: 02400 - 0243f m:08400 - 0847f spi-4 ingress training to out of sync threshold register (p. 111) a:0x0000 b:0x2000 m:0x8000 egress_cal0 0x0500 0x 00 a: 00500-0053f b: 02500-0253f m:08500-0857f spi-4 egress calendar 0 table (p. 111) a:0x0000 b:0x2000 m:0x8000 egress_cal1 0x0600 0x 00 a: 00600-0063f b: 02600-0263f m:08600-0867f spi-4 egress calendar 1 table. (p. 112) spi-4 egress register group a:0x0000 b:0x2000 m:0x8000 egress_reg 0x0800 0x01 a: 00801 b: 02801 m:08801 spi-4 egress configuration register (p. 113) a:0x0000 b:0x2000 m:0x8000 egress_reg 0x0800 0x02 a: 00802 b: 02802 m:08802 spi-4 egress training pa rameter register (p. 113) a:0x0000 b:0x2000 m:0x8000 egress_reg 0x0800 0x03 a: 00803 b: 02803 m:08803 spi-4 egress calendar 0 configuration register (p. 114) module base address block base name block base address register offset indirect register address 0x register description table 18 indirect registers map (part 2 of 8) 84 of 162 october 20, 2006 idt idt88k8483 a:0x0000 b:0x2000 m:0x8000 egress_reg 0x0800 0x04 a: 00804 b: 02804 m:08804 spi-4 egress calendar 1 configuration register (p. 114) a:0x0000 b:0x2000 m:0x8000 egress_reg 0x0800 0x05 a: 00805 b: 02805 m:08805 spi-4 egress status register (p. 115) a:0x0000 b:0x2000 m:0x8000 egress_reg 0x0800 0x06 a: 00806 b: 02806 m:08806 spi-4 egress diagnostics register (p. 115) a:0x0000 b:0x2000 m:0x8000 egress_reg 0x0800 0x07 a: 00807 b: 02807 m:08807 spi-4 egress automatic alignment control register (p. 115) a:0x0000 b:0x2000 m:0x8000 egress_reg, 0x0800 0x08 a: 00808 b: 02808 m:08808 spi-4 egress calen dar switch control register (p. 116) a:0x0000 b:0x2000 m:0x8000 egress_reg 0x0800 0x0b-0x0c a: 0080b b: 0280b m:0880b- 0880c spi-4 egress fill level register (p. 116) a:0x0000 b:0x2000 m:0x8000 egress_reg 0x0800 0x0d-0x0e a: 0080d b: 0280d m:0880d - 0880e spi-4 egress max fill level register (p. 116) a:0x0000 b:0x2000 m:0x8000 egress_reg, 0x0800 0x0f a: 0080f b: 0280f m:0880f reserved a:0x0000 b:0x2000 m:0x8000 spi_timing 0x0900 0x00 a: 00900 b: 02900 m:08900 spi-4 histogram measure launch register (p. 117) a:0x0000 b:0x2000 m:0x8000 spi_timing 0x0900 0x01 a: 00901 b: 02901 m:08901 spi-4 histogram measure status register (p. 117) a:0x0000 b:0x2000 m:0x8000 spi_timing 0x0900 0x02-0x0b a: 00902 - 0090b b: 02902 - 0290b m:08902 - 0890b spi-4 histogram counter register (p. 117) a:0x0000 b:0x2000 m:0x8000 spi_timing 0x0900 0x0c-0x1e a: 0090c - 0091e b: 0290c - 0291e m:0890c - 0891e spi-4 bit alignment result register (p. 118) a:0x0000 b:0x2000 m:0x8000 spi_timing 0x0900 0x2a a: 0092a b: 0292a m:0892a spi-4 egress data lane timing register (p. 118) a:0x0000 b:0x2000 m:0x8000 spi_timing 0x0900 0x2b a: 0092b b: 0292b m:0892b spi-4 egress data control lane timing register (p. 118) module base address block base name block base address register offset indirect register address 0x register description table 18 indirect registers map (part 3 of 8) 85 of 162 october 20, 2006 idt idt88k8483 a:0x0000 b:0x2000 m:0x8000 spi_timing 0x0900 0x2c a: 0092c b: 0292c m:0892c spi-4 egress data clock timing register (p. 119) a:0x0000 b:0x2000 m:0x8000 spi_timing 0x0900 0x2d a: 0092d b: 0292d m:0892d spi-4 egress status timing register (p. 119) a:0x0000 b:0x2000 m:0x8000 spi_timing 0x0900 0x2e a: 0092e b: 0292e m:0892e spi-4 egress status clock timing register (p. 120) a (tm) b (tm) a (mt) b (mt) buffer_ assign tm - 0x1000 mt - 0x1800 0x00-0x3f tm a: 01000 - 0103f b: 03000 - 0303f mt a: 01800 - 0183f b: 03800 - 0383f pfp buffer segment assign table (p. 120) a (tm) b (tm) a (mt) b (mt) packet_ len tm - 0x1100 mt - 0x1900 0x00-0x3f tm a: 01100 - 0113f b: 03100 - 0313f mt a: 01900 - 0193f b: 03900 - 0393f pfp packet length thresholds (p. 121) a (tm) b (tm) a (mt) b (mt) queue_ diagnose tm - 0x1200 mt - 0x1a00 0x00-0x3f tm a: 01200 - 0123f b: 03200 - 0323f mt a: 01a00 - 01a3f b: 03a00 - 03a3f pfp queue diagnose table (p. 121) a (tm) b (tm) a (mt) b (mt) packet_ diagnose tm - 0x1300 mt - 0x1b00 0x00-0x3f tm a: 01300 - 0133f b: 03300 - 0333f mt a: 01b00 - 01b3f b: 03b00 - 03b3f pfp packet diagnose table (p. 121) a (tm) b (tm) a (mt) b (mt) burst_size tm - 0x1400 mt - 0x1c00 0x00-0x3f tm a: 01400 - 0143f b: 03400 - 0343f mt a: 01c00 - 01c3f b: 03c00 - 03c3f pfp egress burst size table (p. 122) a (tm) b (tm) a (mt) b (mt) direction tm - 0x1500 mt - 0x1d00 0x00-0x3f tm a: 01500 - 0153f b: 03500 - 0353f mt a: 01d00 - 01d3f b: 03d00 - 03d3f pfp egress weight and direction register (p. 122) module base address block base name block base address register offset indirect register address 0x register description table 18 indirect registers map (part 4 of 8) 86 of 162 october 20, 2006 idt idt88k8483 a (tm) b (tm) a (mt) b (mt) packet_ mode tm - 0x1600 mt - 0x1e00 0x00-0x3f tm a: 01600 - 0163f b: 03600 - 0363f mt a: 01e00 - 01e3f b: 03e00 - 03e3f pfp egress packet mode control registers (p. 123) pfp tm control register group - 0x1700 pfp mt control register group - 0x1f00 a (tm) b (tm) a (mt) b (mt) tm_pfp_reg mt_pfp_reg tm - 0x1700 mt - 0x1f00 0x00 tm a: 01700 b: 03700 mt a: 01f00 b: 03f00 pfp link number configuration register (p. 123) a (tm) b (tm) a (mt) b (mt) tm_pfp_reg mt_pfp_reg tm - 0x1700 mt - 0x1f00 0x01 tm a: 01701 b: 03701 mt a: 01f01 b: 03f01 pfp buffer management configuration register (p. 123) a (tm) b (tm) a (mt) b (mt) tm_pfp_reg mt_pfp_reg tm - 0x1700 mt - 0x1f00 0x02 tm a: 01702 b: 03702 mt a: 01f02 b: 03f02 pfp queue weighting enable register (p. 124) a (tm) b (tm) a (mt) b (mt) tm_pfp_reg mt_pfp_reg tm - 0x1700 mt - 0x1f00 0x03 tm a: 01703 b: 03703 mt a: 01f03 b: 03f03 pfp flow control register (p. 125) a (tm) b (tm) a (mt) b (mt) tm_pfp_reg mt_pfp_reg tm - 0x1700 mt - 0x1f00 0x04 tm a: 01704 b: 03704 mt a: 01f04 b: 03f04 pfp test register (p. 125) a (tm) b (tm) a (mt) b (mt) tm_pfp_reg mt_pfp_reg tm - 0x1700 mt - 0x1f00 0x05 tm a: 01705 b: 03705 mt a: 01f05 b: 03f05 pfp ingress status monitor register - 1 (p. 126) module base address block base name block base address register offset indirect register address 0x register description table 18 indirect registers map (part 5 of 8) 87 of 162 october 20, 2006 idt idt88k8483 a (tm) b (tm) a (mt) b (mt) tm_pfp_reg mt_pfp_reg tm - 0x1700 mt - 0x1f00 0x06 tm a: 01706 b: 03706 mt a: 01f06 b: 03f06 pfp ingress status monitor register - 2 (p. 126) a (tm) b (tm) a (mt) b (mt) tm_pfp_reg mt_pfp_reg tm - 0x1700 mt - 0x1f00 0x07 tm a: 01707 b: 03707 mt a: 01f07 b: 03f07 pfp ingress status monitor register - 3 (p. 126) a (tm) b (tm) a (mt) b (mt) tm_pfp_reg mt_pfp_reg tm - 0x1700 mt - 0x1f00 0x08 tm a: 01708 b: 03708 mt a: 01f08 b: 03f08 pfp ingress status monitor register - 4 (p. 126) a (tm) b (tm) a (mt) b (mt) tm_pfp_reg mt_pfp_reg tm - 0x1700 mt - 0x1f00 0x09 tm a: 01709 b: 03709 mt a: 01f09 b: 03f09 pfp egress status monitor register - 1 (p. 127) a (tm) b (tm) a (mt) b (mt) tm_pfp_reg mt_pfp_reg tm - 0x1700 mt - 0x1f00 0x0a tm a: 0170a b: 0370a mt a: 01f0a b: 03f0a pfp egress status monitor register - 2 (p. 127) a (tm) b (tm) a (mt) b (mt) tm_pfp_reg mt_pfp_reg tm - 0x1700 mt - 0x1f00 0x0b tm a: 0170b b: 0370b mt a: 01f0b b: 03f0b pfp egress status monitor register - 3 (p. 127) a (tm) b (tm) a (mt) b (mt) tm_pfp_reg mt_pfp_reg tm - 0x1700 mt - 0x1f00 0x0c tm a: 0170c b: 0370c mt a: 01f0c b: 03f0c pfp egress status monitor register - 4 (p. 127) a (tm) b (tm) a (mt) b (mt) tm_pfp_reg mt_pfp_reg tm - 0x1700 mt - 0x1f00 0x0d tm a: 0170d b: 0370d mt a: 01f0d b: 03f0d pfp internal parity error indication register (p. 127) module base address block base name block base address register offset indirect register address 0x register description table 18 indirect registers map (part 6 of 8) 88 of 162 october 20, 2006 idt idt88k8483 a (tm) b (tm) a (mt) b (mt) tm_pfp_reg mt_pfp_reg tm - 0x1700 mt - 0x1f00 0x0e tm a: 0170e b: 0370e mt a: 01f0e b: 03f0e pfp maximum packet length register (p. 128) b: 0x2000 auxiliary 0x0a00 0x00 b: 02a00 auxiliary interface enable register (p. 129) b: 0x2000 auxiliary 0x0a00 0x01 b: 02a01 auxiliary interface configuration register (p. 129) b: 0x2000 auxiliary 0x0a00 0x02 b: 02a02 auxiliary extension buffer configuration register (p. 129) b: 0x2000 auxiliary 0x0a00 0x03 b: 02a03 auxiliary clock monitor status register) (p. 130) b: 0x2000 auxiliary 0x0a00 0x04 b: 02a04 external memory test control register (p. 130) b: 0x2000 auxiliary 0x0a00 0x05 b: 02a05 external memory test results register (p. 131) b: 0x2000 auxiliary 0x0a00 0x07 b: 02a07 auxiliary early backpressure threshold register (p. 131) b: 0x2000 auxiliary 0x0a00 0x08 b: 02a08 auxiliary packet mode configuration register (p. 131) b: 0x2000 auxiliary 0x0a00 0x0e b: 02a0e hstl test register (p. 131) b: 0x2000 auxiliary 0x0a00 0x0f b: 02a0f auxiliary automatic impedance matching control register (p. 132) b: 0x2000 auxiliary 0x0a00 0x12 b: 02a12 auxiliary synchronization status register (p. 132) b: 0x2000 auxiliary 0x0a00 0x13 b: 02a13 auxiliary initialization control register (p. 133) b: 0x2000 prgd 0x0b00 0x00 a: 00b00 enable control register (p. 133) b: 0x2000 prgd 0x0b00 0x01 a: 00b01 feedback configuration register (p. 133) b: 0x2000 prgd 0x0b00 0x02 a: 00b02 bandwidth control register (p. 133) b: 0x2000 prgd 0x0b00 0x03 a: 00b03 b: 02b03 packet length register (p. 134) b: 0x2000 prgd 0x0b00 0x04 a: 00b04 b: 02b04 burst size register (p. 134) b: 0x2000 prgd 0x0b00 0x05 a: 00b05 b: 02b05 random control register (p. 134) b: 0x2000 prgd 0x0b00 0x06 a: 00b06 b: 02b06 lid register (p. 135) b: 0x2000 prgd 0x0b00 0x07 a: 00b07 b: 02b07 synchronization register (p. 135) b: 0x2000 prgd 0x0b00 0x08 a: 00b08 b: 02b08 bit error insertion register (p. 135) a: 0x0000 b: 0x2000 pmon_event 0x0f00 0x00 a: 00f00 b: 02f00 pmon event interrupt indication register (p. 136) a: 0x0000 b: 0x2000 pmon_event 0x0f00 0x01 a: 00f01 b: 02f01 pmon event interrupt enable register (p. 139) module base address block base name block base address register offset indirect register address 0x register description table 18 indirect registers map (part 7 of 8) 89 of 162 october 20, 2006 idt idt88k8483 a: 0x0000 b: 0x2000 pmon_event 0x0f00 0x02- 0x03 a: 00f02 - 00f03 b: 02f02 - 02f03 pmon buffer t-m overflow indication register (p. 140) a: 0x0000 b: 0x2000 pmon_event 0x0f00 0x04- 0x05 a: 00f04 - 00f05 b: 02f04 - 02f05 pmon buffer m-t overflow indication register (p. 141) a: 0x0000 b: 0x2000 pmon_event 0x0f00 0x06- 0x07 a: 00f06 - 00f07 b: 02f06 - 02f07 pmon buffer t-m overflow in terrupt control register (p. 141) a: 0x0000 b: 0x2000 pmon_event 0x0f00 0x08- 0x09 a: 00f08 - 00f09 b: 02f08 - 02f09 pmon buffer m-t overflow interrupt control register (p. 141) a: 0x0000 b: 0x2000 pmon_event 0x0f00 0x0a a: 00f0a b: 02f0a pmon buffer overflow source register (p. 142) a: 0x0000 b: 0x2000 pmon_event 0x0f00 0x0b a: 00f0b b: 02f0b pmon t-m inactive transfer lp field register (p. 142) a: 0x0000 b: 0x2000 pmon_event 0x0f00 0x0c a: 00f0c b: 02f0c pmon m-t inactive transfer lp field register (p. 142) a: 0x0000 b: 0x2000 pmon_event 0x0f00 0x0d a: 00f0d b: 02f0d pmon t-m illegal sop event lid field register (p. 142) a: 0x0000 b: 0x2000 pmon_event 0x0f00 0x0e a: 00f0e b: 02f0e pmon t-m illegal eop event lid field register (p. 142) a: 0x0000 b: 0x2000 pmon_event 0x0f00 0x0f a: 00f0f b: 02f0f pmon m-t illegal sop event lid field register (p. 143) a: 0x0000 b: 0x2000 pmon_event 0x0f00 0x10 a: 00f10 b: 02f10 pmon m-t illegal eop event lid field register (p. 143) a: 0x0000 b: 0x2000 pmon_event 0x0f00 0x11 a: 00f11 b: 02f11 pmon t-m packet cut-down lid field register (p. 143) a: 0x0000 b: 0x2000 pmon_event 0x0f00 0x12 a: 00f12 b: 02f12 pmon m-t packet cut-down lid field register (p. 143) a: 0x0000 b: 0x2000 pmon_lid_cnt 0x0c00 0x00-0x17f a: 00c00 - 00c17 b: 02c00 - 02c17 pmon per lid counter table (p. 144) a: 0x0000 b: 0x2000 pmon_module_ cnt 0x0e00 0x00-0x10 a: 00e00 - 00e10 b: 02e00 - 02e10 pmon per module/interface counter table (p. 144) m: 0x8000 misc 0x0b00 0x00 m: 08b00 miscellaneous registers (p. 145) m: 0x8000 misc 0x0b00 0x01 m: 08b01 pmon 1ms timer register (p. 145) m: 0x8000 misc 0x0b00 0x10-0x12 m: 08b10 - 08b12 gpio direction register (p. 145) m: 0x8000 misc 0x0b00 0x13-0x15 m: 08b13 - 08b15 gpio level register (p. 146) m: 0x8000 misc 0x0b00 0x16-0x18 m: 08b16 - 08b18 gpio link table (p. 146) m: 0x8000 misc 0x0b00 0x30 m: 08b30 version number register (p. 146) m: 0x8000 misc 0x0b00 0x32 m: 08b32 software version register (p. 146) module base address block base name block base address register offset indirect register address 0x register description table 18 indirect registers map (part 8 of 8) 90 of 162 october 20, 2006 idt idt88k8483 direct registers description note: (1) all direct registers are 8 bits wide. (2) unused bits are reserved bits. (3) a read to unused/reserved bits returns 0 while a write is ignored. miscellaneous registers global software reset register microprocessor registers microprocessor mailbox in put fifo data register microprocessor mailbox input fifo length register field read / write bits length reset state description rst r/w 0:0 1 0 this field resets the idt88k8483. reset automatically runs initialization on both software and hardware. read 0: initial state after reset. write 1: reset the chip. note: clocks generated by the idt88k8483 are not affected by a software reset. table 19 global software reset regist er (register offset=0x22) field read / write bits length reset state description data r/w 0:0 - 0:7 8 0 data is written/downloaded to this field, which is a 32 byte ififo, by the host cpu and read by the chip. table 20 microprocessor mailbox input fifo data register (register offset=0x10) field read / write bits length reset state description length r/w 0:0 - 0:5 6 0 this field indicates the number of data bytes that is written to the ?data? field in microprocessor mailbox input fifo data register (p. 90) by the host cpu. table 21 microprocessor mailbox input fifo length register (register offset=0x11) 91 of 162 october 20, 2006 idt idt88k8483 microprocessor mailbox input fifo status register microprocessor mailbox outp ut fifo data register table 23 microprocessor mailbox output fifo data register (register offset=0x12) field read / write bits length reset state description ififo_status r 0:0 1 0 this field indicates whether the host cpu (write side) or the idt88k8483 (read side) has control of the mailbox input ififo. 0:host cpu (write side) has control of ififo. also indicates that the mailbox input fifo is empty and data can be written to the fifo by the host. 1:idt88k8483 (read side) has control of ififo. table 22 microprocessor mailbox input fifo status register (register offset=0x14) field read / write bits length reset state description data r/w 0:0 - 0:7 8 0 data is written/downloaded to this field, which is a 32 byte ofifo, by the idt88k8483 and read by the host cpu. 92 of 162 october 20, 2006 idt idt88k8483 microprocessor mailbox outp ut fifo length register microprocessor mailbox outp ut fifo status register embedded processor state register field read / write bits length reset state description length r/w 0:0 - 0:5 6 0 the number of data bytes written to the ?data? field in the microprocessor mailbox output fifo data register (p. 91) , by the idt88k8483. table 24 microprocessor mailbox outp ut fifo length register (register offset=0x13) field read / write bits length reset state description ofifo_status r 0:0 1 0 indicates whether the host cpu( read side) or idt88k8483 (write side) has con- trol of ofifo. 0: idt88k8483 (write side) has control of ififo. 1: host cpu(read side) has control of ififo. table 25 microprocessor mailbox input fifo status register (register offset=0x15) field read / write bits length reset state description ep_ready r 0:0 1 0 this flag indicates whether the chip is ready to download the firmware binary file from the host cpu. this flag is checked before the host cpu downloads to the idt88k8483. this bit is cleared by reset and will go high after the chip is initialized. 0:not ready for download. 1:ready for application s/w download. ep_running r 0:1 1 0 this flag indicates whether the downloading procedure is finished. 0:download taking place. 1:download finished. chip_ready r 0:2 1 0 this bit indicates that the downloaded software has initiated the chip and user can access it. this bit is set by downloaded software and is cleared by reset. 0:chip not yet ready. 1:chip is ready to be used. table 26 embedded processor state register (register offset=0x16) 93 of 162 october 20, 2006 idt idt88k8483 external microprocessor registers microprocessor indirect access control register microprocessor indirect access data register - 1 field read / write bits length reset state description error r 0:0 - 0:5 6 0 indicates the error code of a read or write operation. 0: no error.operation performed successfully error code- see table 28 below for description of error codes. rwn r/w 0:6 1 0 indicates the initiation of a read or write operation by the obc. 0: a write operation is initiated by the obc. 1: a read operation is initiated by the obc. busy r 0:7 1 0 gives a busy indication if an indirect read or write is initiated. the flag is set until the operation is completed. 0: not busy. 1: busy indication. table 27 microprocessor indirect access control register (register offset=0x1a) error code error 1 reconfiguration attempted without device reset, configuration is allowed only once after reset for this register 2 multiple lps mapped to the same lid 3 multiple lids mapped to the same lp 4 buffer segment assigned exceeds total available segments 5 buffer segment assigned exceeds total number of queue entries available 6 configuration modified while link active 7 undefined address 8 channel limit exceeded 9 to 0x3c reserved 0x3d version mismatch 0x3e protected register 0x3f internal timeout table 28 microprocessor indirect access error codes field read / write bits length reset state description data[0:7] r/w 0:0 - 0:7 8 0 this register contains the first byte of the 4 byte data that is to be written to or read from the indirect register. table 29 microprocessor indirect access data register -1 (register offset=0x1b) 94 of 162 october 20, 2006 idt idt88k8483 microprocessor indirect access data register - 2 microprocessor indirect access data register - 3 field read / write bits length reset state description data[8:15] r/w 0:0 - 0:7 8 0 this register contains the second byte of the 4 byte data that is to be written to or read from the indirect register. table 30 microprocessor indirect access data register - 2 (register offset=0x1c) field read / write bits length reset state description data[16:23] r/w 0:0 - 0:7 8 0 this register contains the third byte of the 4 byte data that is to be written to or read from the indirect register. table 31 microprocessor indirect access data register - 3 (register offset=0x1d) 95 of 162 october 20, 2006 idt idt88k8483 microprocessor indirect access data register - 4 microprocessor indirect a ccess address register - 1 microprocessor indirect a ccess address register - 2 microprocessor indirect a ccess address register - 3 pfp insert/extract registers note: the pfp insert/extract is controlled by obc (on board controller) . data is inserted into the insert fifo by the obc and extrac ted from the extract fifo by the obc. field read / write bits length reset state description data[24:31] r/w 0:0 - 0:7 8 0 this register contains the fourth byte of the 4 byte data that is to be written to or read from the indirect register. table 32 microprocessor indirect access data register - 4 (register offset=0x1e) field read / write bits length reset state description address[0:7] r/w 0:0 - 0:7 8 0 this register contains the first byte of the 2 byte address of the indirect register. table 33 microprocessor indirect access address register - 1 (register offset=0x1f) field read / write bits length reset state description address[8:15] r/w 0:0 - 0:7 8 0 this register contains the second byte of the 2 by te address of the indirect register. table 34 microprocessor indirect access address register - 2 (register offset=0x20) field read / write bits length reset state description address[16:19] r/w 0:0 - 0:3 4 0 reserved. this byte should always be 0x00. table 35 microprocessor indirect access address register - 3 (register offset=0x21) 96 of 162 october 20, 2006 idt idt88k8483 pfp t-m insert control register for module a field read/ write bits length reset state description data_available r/w 0:0 1 0 this field indicates the availability of insert fifo for t-m insertion. read 0: fifo is available read 1: fifo not available write 1: launch data after writing transfer and overhead into the fifo. note: the data_available flag will self clear if fifo is emptied by pfp. this event will be forwarded to interrupt module. table 36 pfp t-m insert control register (register offset=0x0) 97 of 162 october 20, 2006 idt idt88k8483 pfp t-m insert data register for module a pfp t-m extract control register for module a pfp t-m extract data register for module a pfp m-t insert control register for module a pfp m-t insert data register for module a field read/ write bits length reset state description data w 0:0-0:7 8 0 this field holds the data to be written into the insert fifo. table 37 pfp t-m insert data register(register offset=0x1) field read/ write bits length reset state description data_available r/w 0:0 1 0 this bit indica tes the availability of data in the extract fifo. if data is avail- able, then it is extracted from the fifo. read 0: data is not available in the fifo. read 1: data is available in the fifo. write 0: clears the extract fifo. note: after data is extracted from the fifo, a transfer extract event will be forwarded to the interrupt module. table 38 pfp t-m extract contro l register (register offset=0x2) field read/ write bits length reset state description data r 0:0-0:7 8 0 this field holds the content read from the fifo. table 39 pfp t-m extract data register (register offset=0x3) field read/ write bits length reset state description data_available r/w 0:0 1 0 this field indicates the av ailability of insert fi fo for m-t insertion. read 0: fifo is available read 1: fifo not available write 1: launch data after writing transfer and overhead into the fifo. note: the data_available flag will self clear if fifo is emptied by pfp. this event will be forwarded to interrupt module. table 40 pfp m-t insert control register (register offset=0x4) field read/ write bits length reset state description data w 0:0-0:7 8 0 the content to be inserted into the insert fifo is written into this field. table 41 pfp m-t insert data register (register offset=0x5) 98 of 162 october 20, 2006 idt idt88k8483 pfp m-t extract control register for module a pfp m-t extract data register for module a interrupt registers primary interrupt in dication register field read/ write bits length reset state description data_available r/w 0:0 1 0 this bit indi cates the availability of data in the extract fifo. if data is available, then it is extracted from the fifo. read 0: data is not available in the fifo. read 1: data is available in the fifo. write 0: clears the fifo. note: after data is extracted from the fi fo, a transfer extract event will be forwarded to the interrupt module. table 42 pfp m-t extract control register (register offset=0x6) field read/ write bits length reset state description data r 0:0-0:7 8 0 this field holds the content extracted from the fifo. table 43 pfp m-t extract data register (register offset=0x7) field read / write bits length reset state description module_a r/w 0:0 1 0 this field capture events in module a. read 0: normal operation of module a. read 1: an event is captured in module a. write 1: this field is cleared. module_b r/w 0:1 1 0 this field capture events in module b. read 0: normal operation of module b. read 1: an event is captured in module b. write 1: this field is cleared. common r/w 0:2 1 0 this field capture events in module m. read 0: normal operation of module m. read 1: an event is captured in module m. write 1: this field is cleared. table 44 primary interrupt in dication register (register offset=0x08) 99 of 162 october 20, 2006 idt idt88k8483 primary interrupt enable register note: please refer to interrupt scheme (p. 64) for an explanation of the interrupt scheme. field read / write bits length reset state description module_a_en r/w 0:0 1 0 this field enables an interrupt to be generated if an event is captured in module_a field in primary interrupt indication register (p. 98) . 0: disable. 1: enable. module_b_en r/w 0:1 1 0 this field enables an interrupt to be generated if an event is captured in module_b field in primary interrupt indication register (p. 98) . 0: disable. 1: enable. common_en r/w 0:2 1 0 this field enables an interrupt to be generated if an event is captured in common field in primary interrupt indication register (p. 98) . 0: disable. 1: enable. table 45 primary interrupt enable register (register offset=0x09) 100 of 162 october 20, 2006 idt idt88k8483 secondary interrupt module a indication register secondary interrupt modu le a enable register field read / write bits length reset state description spi-mt extract r/w 0:0 1 0 this bit indicates when a pfp m-t extraction event takes place in module a. read 0: no extraction. read 1: an extraction event has occurred in the pfp m-t locker in module a. write 1: clear this field. spi-tm extract r/w 0:1 1 0 this bit indicates when a pfp t-m extraction event takes place in module a. read 0: no extraction. read 1: an extraction event has occurred in the pfp t-m locker in module a. write 1: clear this field. spi-tm insert r/w 0:2 1 0 this bit indicates when a pfp t-m insertion event takes place in module a. read 0: no extraction. read 1: an insertion event has occurred in the pfp t-m locker in module a. write 1: clear this field. spi-mtinsert r/w 0:3 1 0 this bit indicates when a pfp m-t insertion event takes place in module a. read 0: no extraction. read 1: an insertion event has occurred in the pfp m-t locker in module a. write 1: clear this field pmon r 0:4 1 0 indicates if a pmon event has occurred. table 46 secondary module indi cation register (register offset=0x0a.) field read / write bits length reset state description spi- mtextract_en r/w 0:0 1 0 this field enables an interrupt to be generated if an event is captured in ?spi-mt extract? field in the secondary interrupt module a indication register (p. 100) 0: disable. 1: enable. spi- tmextract_en r/w 0:1 1 0 this field enables an interrupt to be generated if an event is captured in ?spi-tm extract? field in the secondary interrupt module a indication register (p. 100). 0: disable. 1: enable. spi-tminsert_en r/w 0:2 1 0 this field enables an interrupt to be generated if an event is captured in ?spi-tm insert? field in the secondary interrupt module a indication register (p. 100) . 0: disable. 1: enable. spi-mtinsert_en r/w 0:3 1 0 this field enables an interrupt to be generated if an event is captured in ?spi-mt insert? field in the secondary interrupt module a indication register (p. 100) . 0: disable. 1: enable. pmon_en r/w 0:4 1 0 this field enables an interrupt to be generated if an event is captured in pmon field in secondary interrupt module a indication register (p. 100) . 0: disable. 1: enable. note: writing a 1 to any field in this register, causes an interrupt to be generated based on the occurrence of that particular even t indicated in the corresponding field in table 46 . the interrupt appears as an active low on the intb pin in the microprocessor interface. table 47 secondary module enable register (register offset=0x0b) 101 of 162 october 20, 2006 idt idt88k8483 secondary interrupt module b indication register secondary interrupt modu le b enable register field read / write bits length reset state description reserved 0:0 - 0:4 pmon r 0:4 1 0 indicates if a pmon event has occurred. table 48 secondary interrupt module b i ndication register(reg ister offset=0xc) field read / write bits length reset state description reserved 0:0 - 0:3 4 pmon_en r 0:4 1 0 this field enables an interrupt to be generated if an event is captured in pmon field in secondary interrupt module b indication register (p. 101) . 0: disable. 1: enable. table 49 secondary interrupt module b enable register (r egister offset=0xd) 102 of 162 october 20, 2006 idt idt88k8483 secondary interrupt comm on indication register field read / write bits length reset state description timebase r/w 0:0 1 0 this fiel d indicates an event captured in the timebase. read 0: no event is generated. read 1: an event is generated by a timebase trigger. write 1: clear the field. indirect_acc r/w 0:1 1 0 this field indicates an event captured in the indirect access. read 0: no event is generated. read 1: an event is generated due to an invalid indirect access sequence. write 1: clear the field. i_fifo_ready r/w 0:2 1 1 this field indicates when the embedded processor is ready to accept data through the i_fifo read 0: i_fifo not ready to accept data. read 1: i_fifo ready to accept data. write 1: resets the field. i_fifo_oflow r/w 0:3 1 0 this field indicates if the mailbox i_fifo is oveflowed. read 0: no overflow in mailbox i_fifo. read 1: overflow in mailbox i_fifo. an attempt to write more than 32 bytes generates this interrupt. write 1: clears this field. o_fifo_msg r/w 0:4 1 0 this field indicates when the embedded processor has data in its mailbox o_fifo read 0: no data in present in o_fifo. read 1: data is present in o_fifo. write 1: resets the bit. soc r/w 0:5 1 0 soc trigger 10ms r/w 0:6 1 0 this field generates a 10ms timer event based on the 1ms timer. read 0: 10ms timer event is not generated. read 1: 10ms timer event is generated. write 1: resets the field. table 50 interrupt seconda ry common indication regist er (register offset=0xe) 103 of 162 october 20, 2006 idt idt88k8483 secondary interrupt common enable register field read / write bits length reset state description timebase_en r/w 0:0 1 0 this field enables an interrupt to be generated if an event is captured in ?timebase? field in the secondary interrupt common indication register (p. 102) .the interrupt appears as an active low on the intb pin in the microprocessor interface. 0: disable. 1: enable. indirect_acc_en r/w 0:1 1 0 this field enables an interrupt to be generated if an event is captured in ?indirect_acc? field in the secondary interrupt common indication register (p. 102) .the interrupt appears as an active low on the intb pin in the microprocessor interface. 0: disable. 1: enable. i_fifo_ready_en r/w 0:2 1 0 this field enables an interrupt to be generated if an event is captured in ?i_fifo_ready? field in the secondary interrupt common indication register (p. 102) .the interrupt appears as an active low on the intb pin in the microprocessor interface. 0: disable. 1: enable. i_fifo_oflow_en r/w 0:3 1 0 this field enables an interrupt to be generated if an event is captured in ?i_fifo_oflow? field in the secondary interrupt common indication register (p. 102) .the interrupt appears as an active low on the intb pin in the microprocessor interface. 0: disable. 1: enable. o_fifo_msg_en r/w 0:4 1 0 this field enables an interrupt to be generated if an event is captured in o_fifo_msg field in the secondary interrupt common indication register (p. 102) .the interrupt appears as an active low on the intb pin in the microprocessor interface. 0: disable. 1: enable. soc_en r/w 0:5 1 0 this field enables an interrupt to be generated if an event is captured in ?soc? field in the secondary interrupt common indication register (p. 102) .the interrupt appears as an active low on the intb pin in the microprocessor interface. 0: disable. 1: enable. 10ms_en r/w 0:6 1 0 this field enables an interrupt to be generated if an event is captured in ?10ms? field in the secondary interrupt common indication register (p. 102) .the interrupt appears as an active low on the intb pin in the microprocessor interface. 0: disable. 1: enable. note: writing a 1 to any field in this register, causes an interrupt to be generated based on the occurrence of that particular even t indicated in the corresponding field in table 50 . the interrupt appears as an active low on the intb pin in the microprocessor interface. table 51 interrupt secondary common en able register (register_offset=0xf) 104 of 162 october 20, 2006 idt idt88k8483 indirect registers description note: (1) all indirect registers are 32 bits wide. (2) treat unused bits as reserved bits. (3) a read to unused/reserved bits returns 0 while a write is ignored. clock registers mclk divider sticky register clock control input status register field read / write bits length reset state description n r/w 0:0-0:1 2 11 selects the frequency of the mclk. 00: f/2. 01: f/3. 10: f/4. 11: f/5. note: (1) ?sticky? means that the register value does not change during software reset. (2) mclk is generated by t he clock generator type m and is used for generic interface, the pfp block and the pmon block.please refer to figure 36 clock generator type m p.70?clock generator type m? on page 70 for mclk discussion . table 52 mclk divider sticky register ( block base=0x0a00, register offset=0x00 ) field read / write bits length reset state description div_four r 0:0 1 pin input reflects the state of the external configuration signal div4. this signal selects the prescaler frequency to divide by 1 or 4. 0: configures the prescaler frequency to divide by 1. full rate. 1: configures the prescaler frequency to divide by 4. quarter rate. ck_sel_a r 0:1 1 pin input reflects the value of the external configuration signal spi4a_clk_sel. this signal configures the divider1 frequency to divide by 2 or 8. 0: divide by 2. 1: divide by 8. ck_sel_b r 0:2 1 pin input reflects the value of the external configuration signal spi4b_clk_sel. this signal configures the divider1 frequency to divide by 2 or 8. 0: divide by 2. 1: divide by 8. ck_sel_m r 0:3 1 pin input reflects the value of the external configuration signal spi4m_clk_sel. this signal configures the divider1 frequency to divide by 2 or 8. 0: divide by 2. 1: divide by 8. note: please refer to clk_sel signals configuration (p. 69) and figure 36 clock generator type m p.70 for clock description. table 53 clock control input status register ( block base=0x0a00, register offset=0x01 ) 105 of 162 october 20, 2006 idt idt88k8483 spi-4 registers spi-4 ingress lp to lid mapping table spi-4 ingress calendar 0 table spi-4 ingress calendar 1 table field read / write bits length reset state description n r/w 0:0 - 0:5 6 0 lid number.this field maps the lp to the lid in the pfp and can take any 1 of 64 possible lid values. the lp number is the register offset. refer to figure 3 and fig- ure 4 for lid information. p r/w 0:6 1 0 selects module a or module b ingress, valid for main. 0:module a. 1:module b. reserved r 0: 7 1 0 reserved bit. enable r/w 1:0 1 0 enables or disables this lp connection to the lid. 0 : disable. 1:enable. table 54 spi-4 ingress lp to lid mapping table ( block base=0x0000, regi ster offset=0x00-0xff ) field read / write bits length reset state description lp r/w 0:7 8 0xff the lp value programmed schedules a status channel update according to the calendar sequence. note: (1)there are 128 table entries for spi-4 main interf ace and 64 table entries for spi-4 tributary interface. (2)the idt88k8483 and the attac hed device must have identical calendar s for ingress and the attached egress device. table 55 spi-4 ingress calendar 0 table ( block base=0x0100, regi ster offset=0x00-0x3f/0x7f ) field read / write bits length reset state description lp r/w 0:7 8 0xff the lp value programmed schedules a status channel update according to the calendar sequence. note: (1)there are 128 table entries for spi-4 main interf ace and 64 table entries for spi-4 tributary interface. (2)the idt88k8483 and the attac hed device must have identical calendar s for ingress and the attached egress device. table 56 ingress calendar 1 table ( block base=0x0200, register offset=0x00-0x3f/0x7f ) 106 of 162 october 20, 2006 idt idt88k8483 spi-4 interface enable register spi-4 ingress configuration register field read / write bits length reset state description spi4_en r/w 0:0 1 0 this bit enables/disables the spi-4 interface ingress path. the spi-4 ingress path is disabled during reset and while configuring the port and is then enabled for normal use. 0: disable. 1: enable. spi4_pdn r/w 0:1 1 0 spi4 interface power down mode. 0:power up. 1:power down or disable the spi4 lvds i/o, except the clock. note: (1) the spi4 interface has to be configured before enabling the interface table 57 spi-4 interface enable register ( block base= 0x0300, register offset=0x00 ) field read / write bits length reset state description i_insync_thr r/w 0:0-0:4 5 0x1f the number of consecutive error free dip-4 that need to be detected before the spi-4 ingress data channel is synchronized. the actual number of error free dip 4 that need to be detected is i_insync_thr+1. i_clk_edge r/w 0:5 1 1 indicates the active edge of the status clock in lvttl mode. 0:the status information is output at the rising edge of the status clock. 1:the status information is output at the falling edge of the status clock . i_low r/w 0:6 1 1 this bit should be set to ?0? or ?1?depending on the frequency of the ingress status clock output when the status channel is selected to run in lvds mode (lvds_sta bit intable 62 indicates a ?1?) 0: isclk clock is higher than or equal to 200 mhz. 1: isclk clock is lower than 200 mhz. reserved r 0:7 1 0 reserved bits. i_outsync_thr r/w 1:0-1:3 4 0xf indicates the number of consecutive dip4 errors that need to be detected before the ingress data channel changes from in sync state to out of sync state note: please refer to figure 16 for an illustration of out of sync and in sync state. table 58 spi-4 ingress configuration register ( block base=0x0300, register offset=0x01 ) 107 of 162 october 20, 2006 idt idt88k8483 spi-4 ingress traini ng parameter register spi-4 ingress calendar 0 configuration register . field read / write bits length reset state description fifo_max_t r/w 0:0-2:7 24 0 the spi-4 ingress fifo_max_t field is the maximum time interval between scheduling of training sequences on the fifo status path interface. the units are in 2 8 spi-4 data cycles. alpha_fifo r/w 3:0-3:7 8 0 the spi-4 ingress alpha_fifo field is the number of repetitions of the status training sequence that must be scheduled every fifo_max_t cycles. the value for alpha used is actually one more than the alpha_fifo value programmed into the alpha_fifo field. note: the purpose of the fifo status path training sequence is for the deskew of bit arrival times on the fifo status and control lin es. table 59 spi-4 ingress training parameter register ( block base=0x0300, register offset=0x02 ) field read / write bits length reset state description i_cal_m r/w 0:0-0:7 8 0x01 the i_cal_m value programmed defines the number of times the calendar 0 sequence is repeated before a dip-2 parity and ?1 1? framing words are inserted 1 . the actual calendar_m 3 value used is one more than the value programmed into the i_cal_m field. i_cal_len r/w 1:0-1:6 7 0x7 indicates the length of the ingress calendar 0 2 .the actual calendar length calendar_len 3 is i_cal_len+1. in lvttl mode, the i_cal_len can be programmed with any value. in lvds mode, the i_cal_len should be programmed with 4n-1, where n is an integer. note: 1 if the i_csw_en bit in spi4 ingress calendar switch control register (p. 109) is set to 1,then the i_cal_m value defines the number of times the calendar sequence is repeated before a dip2 parity,?1 1? framing word and calendar selection word are inserted. 2 the calendar length calendar_m must be at least as large as the number of active spi-4 ingress lps. calendar_m must match the n umber of entries in the spi-4 ingress calendar 0 table (p. 105) 3 calendar_len and calendar_m are described in the oif spi-4 implementation agreement (oif-spi-4-02.1). table 60 spi-4 ingress calendar 0 configuration register ( block base=0x0300, register offset=0x03 ) 108 of 162 october 20, 2006 idt idt88k8483 spi-4 ingress calendar 1 configuration register spi-4 ingress st atus register field read / write bits length reset state description i_cal_m r/w 0:0-0:7 8 0x01 the i_cal_m value programmed defines the number of times the calendar 1 sequence is repeated before a dip-2 parity and ?1 1? framing words are inserted 1 . the actual calendar_m 3 value used is one more than the value programmed into the i_cal_m field. i_cal_len r/w 1:0-1:6 7 0x7 indicates the length of the ingress calendar 1 2 . the actual calendar length calendar_len 3 is i_cal_len+1. in lvttl mode, the i_cal_len can be programmed with any value. in lvds mode, the i_cal_len should be programmed with 4n-1, where n is an integer. note: 1 if the i_csw_en bit in spi4 ingress calendar switch control register (p. 109) is set to 1,then the i_cal_m value defines the number of times the calendar sequence is repeated before a dip2 parity,?1 1? framing word and calendar selection word are inserted. 2 the calendar length calendar_m must be at least as large as the number of active spi-4 ingress lps. calendar_m must match the n umber of entries in the spi-4 ingress calendar 1 table (p. 105) 3 calendar_len and calendar_m are described in the oif spi-4 implementation agreement (oif-spi-4-02.1). table 61 spi-4 ingress calendar 1 configuration register ( block base=0x0300, register offset=0x04 ) field read / write bits length reset state description i_syncv r 0:0 1 0 describes the synchronization state of the spi-4 ingress data path. refer to figure 16 spi-4 ingress state machine p.44 for an illustration of out of sync and in sync state. 0:spi-4 ingress data path is out of synchronization 1:spi-4 ingress data path is in synchronization i_dsk_oor r 0:1 1 0 indicates the state of the de-skew block in the ingress datapath.refer to figure 15 spi-4 ingress block diagram p.43 for de-skew overview. 0: spi-4 ingress data path de-skew is within range. 1: spi-4 ingress data path de-skew is out of range. dclk_av r 0:2 1 0 describes the availability state of the spi-4 ingress data clock. 0:spi-4 ingress data clock is not available. 1:spi-4 ingress data clock is available. lvds_sta r 0:3 1 x the spi-4 ingress status channel mode (lvds/lvttl) is configured by lvdssta pin and this pin?s level is indicated in the lvds_sta field. 0:lvttl mode. 1:lvds mode. table 62 spi-4 ingress status register ( block base=0x0300, register offset=0x05 ) 109 of 162 october 20, 2006 idt idt88k8483 spi-4 ingress diagnostics register spi-4 ingress automatic a lignment control register spi4 ingress calendar switch control register table 65 spi-4 ingress calendar sw itch control register ( block base=0x0300, register offset=0x08 ) field read / write bits length reset state description i_force_train r/w 0:0 1 0 this field is used to force continuous training on the spi-4 ingress status interface. 0:normal status channel operation. 1:force continuous training on the spi-4 ingress status interface. i_err_ins r/w 0:1 1 0 this field is used to insert the number of dip-2 errors on the spi-4 ingress status interface programmed into the i_dip_num field. after the dip-2 errors are inserted, the i_err_ins field will clear itself. 0:normal status channel operation. 1:insert dip-2 errors on the spi-4 ingress status interface. i_dip_num r/w 0:2-0:5 4 0 this field is used to program the number of dip-2 errors to be inserted when the field i_err_ins is set to ?1?. the number programmed should be less than 16. note: the purpose of the status channel training sequence is for the deskew of status and clock signals and for the alignment between the 2 status signals. table 63 spi-4 ingress diagnostics register ( block base=0x0300, register offset=0x06 ) field read / write bits length reset state description auto_align r/w 0:0 1 0 this field enables or disables automatic alignment for the incoming lvds data bits in the data path. this register is used for test purposes. 0:auto alignment is used for test mode. 1:auto alignment is automatic. table 64 spi-4 ingress automatic al ignment control register ( block base=0x0300, register offset=0x07 ) field read / write bits length reset state description i_csw_en r/w 0:0 1 0 the i_csw_en field is used to enable the switching of active calendars and works together with cal_sel.refer to table 66 for calendar selection. cal_sel r/w 0:1 1 0 this field is used to select calendar_0 or calendar_1. this bit is valid only if i_csw_en is set to 1. refer to table 66 for calendar selection. i_dip_csw r/w 0:2 1 1 this field describes the dip-2 computation method based on the setting of i_csw_en.please refer totable 67 for bit setting. note: refer to the oif spi-4 implementation agreement (oif-spi-4-02.1) for more details about calendar implementation. 110 of 162 october 20, 2006 idt idt88k8483 table 66 ingress calendar switch register: bit cal_sel table 67 ingress calendar switch register: bit i_dip_csw spi-4 ingress fill level register there are 2 registers for spi-4 main interface. spi-4 ingress max fill level register there are 2 registers for spi-4 main interface. cal_sel i_csw_en description 0 1 selects calendar 0.calendar selection word is fixed to 01b and is placed after framing pattern. 1 1 selects calendar 1.calendar selection word is fixed to 10b and is placed after framing pattern. x 0 selects calendar 0. i_dip_csw i_csw_en description x 0 dip2 is computed over all preceding status indications after last ?11? framing pattern. 1 1 dip2 is computed over all preceding status indications after last ?11? framing pattern, including the calendar selection word, which is fixed at 10b. 0 1 dip2 is computed over all preceding status indications after last ?11? framing pattern, excluding the calendar selection word. field read / write bits length reset state description fill_cur r 0:0-0:5 6 0x0 indicates the current fill level of the ingress locker. since this is a real-time register, the value read from it will change rapidly and is used for internal diagnostics only. table 68 spi-4 ingress fill level register ( block base=0x0300, register offset=0x0b-0x0c ) field read / write bits length reset state description fill_max r/clear 0:0-0:5 6 0x0 indicates the maximum fill level of the ingress locker since the time of the last read of this register. this register is cleared after reading. table 69 spi-4 ingress max fill level register ( block base=0x0300, register offset=0x0d-0x0e 111 of 162 october 20, 2006 idt idt88k8483 spi-4 ingress watermark register there are 2 registers for spi-4 main interface. spi-4 ingress training to out of sync threshold register spi-4 egress lid to lp mapping table there are 128 table entries for spi-4 main interfac e and 64 table entries for spi-4 tributary interface. spi-4 egress calendar 0 table there are 128 table entries for spi-4 main egress and 64 table entries for spi-4 tributary egr ess calendar_0 to schedule the up dating of the status channel lps to the attached device field read / write bits length reset state description watermark r/w 0:0-0:4 5 0x0d sets the watermark value per pfp.this indicates that if ?watermark? number of ingress lockers are full, then backpressure will be initiated for all lids on a spi-4 ingress interface. note:(1) 0x1f is the highest watermark that can be set, meaning that the ingress buffer will be full before backpressure will b e initiated on a spi-4 ingress inter face pfp. a watermark field value of 0x0f is used to set a watermark for a half-full ingress buffer before tripp ing backpressure. (2) per lid backpressure is set in fields thr_star v and thr_hung in the pfp buffer segment assign table (p. 120) table 70 spi-4 ingress watermark register ( block base=0x0300, register offset=0x0f-0x10 ) field read / write bits length reset state description strt_train r/w 0:0-0:7 8 0 !=0: if this field is not equal to zero, then the ingress interface goes out of sync if more than strt_train times consecutive training pattern is received on its data channel. table 71 ingress training to out of sy nc threshold registe(block base=0x0300,register offset=0x13) field read / write bits length reset state description lp r/w 0:0-0:7 8 0 lp number. lid to lp map is used to map a lid used internally to a spi-4 egress logical port. en r/w 1:0 1 0 the en bit is used to enable or disable the connection of a lid to an lp. 0=lp is disabled 1=lp is enabled note: the lid number is equal to the register offset. table 72 spi-4 egress lid to lp mapping table ( block base=0x0400, register offset=0x00-0x3f/0x7f ) field read / write bits length reset state description lp r/w 0:0-0:7 8 0xff the logical port value programmed in this field, schedules a status channel update according to the calendar sequence. table 73 spi-4 egress calendar 0 table ( block base=0x0500, register offset=0x00-0x3f/0x7f ) 112 of 162 october 20, 2006 idt idt88k8483 spi-4 egress calendar 1 table . there are 128 table entries for spi-4 main egress and 64 table entries for spi-4 tributary egr ess calendar_1 to schedule the up dating of the status channel lps to the attached device field read / write bits length reset state description lp r/w 0:0-0:7 8 0xff the logical port value programmed in this field schedules a status channel update according to the calendar sequence. table 74 spi-4 egress calendar 1 table ( block base=0x0600, register offset=0x00-0x3f /0x7f) 113 of 162 october 20, 2006 idt idt88k8483 spi-4 egress configuration register spi-4 egress training parameter register field read / write bits length reset state description e_insync_thr r/w 0:0-0:4 5 0x1f the number of consecutive error free dip 2 required to make the egress status channel state machine transition from out of sync to in sync.the actual number of error free dip 2 that need to be detected is e_outsync_thr+1. e_clk_edge r/w 0:5 1 0 this field controls the edge of the status clock in lvttl mode, at which the status information will be sampled. 0:sampling is done at rising edge. 1:sampling is done at falling edge. e_low r/w 0:6 1 1 for optimum device performance, this bit should be set to ?0? or ?1? depending on the spi-4 egress data clock frequency. 0: edclk is higher than or equal to 200 mhz. 1: edclk is lower than 200 mhz. nostat r/w 0:7 1 0 the nostat bit enables the no status channel option. once nostat is set, the status channel is ignored. there is no dip-2 error checking, and no status channel updating. the received status is fixed to starving. the data channel is put into the in sync state. 0:normal status channel operation. 1:no status channel option is selected. e_outsync_thr r/w 1:0-1:3 4 0xf the number of consecutive dip 2 errors needed for the egress state to transition from in sync to out of sync.the actual number of dip 2 errors that need to be detected is e_insync_thr+1. note: please refer to spi-4 ingress state machine (p. 44) for an illustration of out of sync and in sync state. table 75 spi-4 egress configuration register ( block base=0x0800, register offset=0x01 ) field read / write bits length reset state description data_max_t r/w 0:0-2:7 24 0 the spi-4 egress data_max_t field is the maximum time interval between scheduling of training sequences on the egress data path interface. the unit is in 2 8 spi-4 data cycles. alpha r/w 3:0-3:7 8 0 the spi-4 egress alpha field is the number of repetitions of the data training sequence that must be scheduled every data_max_t cycles. the value for alpha used is actually one more than the alpha value programmed into the alpha field. note: the purpose of the data path training sequence is for the deskew of bit arrival times on the data and control lines. table 76 spi-4 egress training parameter register ( block base=0x0800, register offset=0x02 ) 114 of 162 october 20, 2006 idt idt88k8483 spi-4 egress calendar 0 configuration register spi-4 egress calendar 1 configuration register field read / write bits length reset state description e_cal_m r/w 0:0-0:7 8 0x01 the e_cal_m value programmed defines the number of times the calendar sequence is repeated before a dip-2 parity and ?1 1? framing words are inserted 1 . the actual calendar_m value used is one more than the value programmed into the e_cal_m field. e_cal_len r/w 1:0-1:6 7 0x07 this field specifies the egress calendar 0 length. in lvttl mode, the e_cal_len can be programmed with any value. in lvds mode, it should be programmed with 4n-1, where n is an integer.indicates the length of the egress calendar 0 2 . the actual calendar length calendar_len 3 is e_cal_len+1. note: 1 if the e_csw_en bit in spi-4 egress calendar switch control register (p. 116) is set to 1,then the e_cal_m va lue defines the number of times the calendar sequence is repeated before a dip2 parity,?1 1? framing word and calendar selection word are inserted. 2 the calendar length calendar_m must be at least as large as the number of active spi-4 egress lps. calendar_m must match the nu mber of entries in the spi-4 egress calendar 0 table (p. 111) 3 calendar_len and calendar_m are described in the oif spi-4 implementation agreement (oif-spi-4-02.1). table 77 spi-4 egress calendar 0 configuration register ( block base=0x0800, register offset=0x03 ) field read / write bits length reset state description e_cal_m r/w 0:0-0:7 8 0x01 the e_cal_m value programmed defines the number of times the calendar sequence is repeated before a dip-2 parity and ?1 1? framing words are inserted 1 . the actual calendar_m value used is one more than the value programmed into the e_cal_m field. e_cal_len r/w 1:0-1:6 7 0x07 this field specifies the egress calendar 1 length. in lvttl mode, the e_cal_len can be programmed with any value. in lvds mode, it should be programmed with 4n-1, where n is an integer. indicates the length of the egress calendar 1 2 . the actual calendar length calendar_len 3 is e_cal_len+1. note: 1 if the e_csw_en bit in spi-4 egress calendar switch control register (p. 116) is set to 1,then the e_cal_m va lue defines the number of times the calendar sequence is repeated before a dip2 parity,?1 1? framing word and calendar selection word are inserted. 2 the calendar length calendar_m must be at least as large as the number of active spi-4 ingress lps. calendar_m must match the n umber of entries in the spi-4 egress calendar 1 configuration register (p. 114) 3 calendar_len and calendar_m are described in the oif spi-4 implementation agreement (oif-spi-4-02.1). table 78 spi-4 egress calendar 1 configuration register ( block base=0x0800, register offset=0x04 ) 115 of 162 october 20, 2006 idt idt88k8483 spi-4 egress status register spi-4 egress diagnostics register spi-4 egress automatic al ignment cont rol register field read / write bits length reset state description e_syncv r 0:0 1 0 describes the synchronization state of the egress status channel state machine. 0:spi-4 egress status channel is out of synchronization. 1:spi-4 egress status channel is in synchronization. e_dsk_oor r 0:1 1 0 indicates the state of the de-skew block in the egress status path.refer to figure 17 for de-skew overview. 0:spi-4 egress status path de-skew is within range. 1:spi-4 egress status path de-skew is out of range. sclk_av r 0:2 1 0 describes the availability state of t he spi-4 egress status channel clock.this field is cleared if there is no status clock available on lvds or lvttl input on a 2048 mclk hopping window. 0:spi-4 egress status channel clock not available. 1:spi-4 egress status channel clock is available. table 79 spi-4 egress status register ( block base=0x0800, register offset=0x05 ) field read / write bits length reset state description e_force_train r/w 0:0 1 0 this field is used to force continuous training on the spi-4 egress datapath. 0:normal datapath operation. 1:force continuous training on the spi-4 egress datapath. e_err_ins r/w 0:1 1 0 inserts consecutive dip-4 error on egress datapath based on the number programmed in the e_dip_num field. after the dip-4 errors are inserted, the e_err_ins field will clear itself. 0: normal datapath operation. 1: insert dip-4 error on the spi-4 egress datapath. e_dip_num r/w 0:2-0:5 4 0 this field is used to program the number of dip-4 errors to be inserted when the field e_err_ins is set to ?1?. this number should be less than 16. bit_delay r/w 0:6-0:7 2 0 the bit_delay field is used to delay spi-4 egress data bit line 0 by the number of bits programmed into the bit_delay field. this may be used for diagnostics. note: the purpose of the data path training sequence is for the deskew of data and clock signals and for the alignment between the 1 6 data signals. table 80 spi-4 egress diagnostics register ( block base=0x0800, register offset=0x06 ) field read / write bits length reset state description auto_align r/w 0:0 1 0 this field enables or disables automatic alignment for the incoming lvds data bits in the status path.this register is used for test purposes. 0:auto alignment is disabled. 1: alignment is automatic. table 81 spi-4 egress automatic alignment control regi ster (block base=0x0800, register offset=0x07 ) 116 of 162 october 20, 2006 idt idt88k8483 spi-4 egress calendar sw itch control register spi-4 egress fill level register there are two registers for spi-4 main interface. spi-4 egress max fill level register there are two registers for spi-4 main interface. field read / write bits length reset state description e_csw_en r/w 0:0 1 0 the engress calendar switch enable bit is used to enable the switching of the active calendars following the reception of the calendar selection word on the status channel. 0:egress calendar switch is disabled. only spi-4 egress calendar 0 is used. 1:egress calendar switch is enabled. calendar 0 or calendar 1 will automatically be selected depending on the value of the received calendar selection words. cal_id r 0:1 1 0 msb of calendar id word e_dip_csw r/w 0:2 1 1 this field describes the dip-2 computation method of the received dip-2 on the sta- tus channel. it is based on the selection of calendar 0 or calendar 1.refer to table 67 page 110 for a detailed explanation. note: refer to the oif spi-4 implementation agreement (oif-spi-4-02.1) for more details about calendar implementation. table 82 spi-4 egress calendar switch control regist er (block base = 0x0800, register offset=0x08 ) field read / write bits length reset state description fill_cur r 0:0-0:3 4 0 indicates the current fill level of the egress locker. since this is a real-time register, the value read from it will change rapidly and is used for internal diagnostics only table 83 spi-4 egress fill level regi ster (block base=0x0800, register offset = 0x0b and 0x0c ) field read / write bits length reset state description fill_max r/c 0:0-0:3 4 0 indicates the maximum fill level of the egress locker since the time of the last read of this register. this register is cleared after reading. table 84 spi-4 egress max fill level register (block base =0x0800, register offset = 0x0d and 0x0e ) 117 of 162 october 20, 2006 idt idt88k8483 spi-4 histogram measure launch register spi-4 histogram measu re status register spi-4 histogram counter register field read / write bits length reset state description lane r/w 0:0-0:4 5 0 lane field selects the spi-4 ingress datapath lanes, control lane or spi-4 egress associated status channel lanes that will use manual bit alignment. 0:spi-4 ingress data0 lane selected for measurement. x:spi-4 ingress datax lane selected for measurement. 15:spi-4 ingress data15 lane selected for measurement. 16:spi-4 ingress ctl selected for measurement. 17:spi-4 egress status 0 lane selected for measurement. 18:spi-4 egress status 1 lane selected for measurement. note: the manual bit alignment is a edge transition histogram measure process. please refer to figure 15(ingress block diagram) and subsequent description for histogram overview. in normal operation bit alignment is automatic and these registers are not used. table 85 spi-4 histogram measure launch register (block base=0x0900 register offset=0x00 ) field read / write bits length reset state description busy r 0:0 1 0 this field is used to observe when the lane process in table 85 is busy for manual lane assignment procedures and is self cleared when the process completes.the busy field is intended for diagnostics only and is not needed for normal operation. 0:lane process is complete. 1:lane process is busy. error r 0:1 1 0 this field indicates the result after the manual bit alignment (lane process) is com- pleted. 0:successful measure. this field is auto cleared when a new measure is launched. 1:aborted indication. table 86 spi-4 histogram measure status register (block base=0x0900 register offset=0x01 ) field read / write bits length reset state description c[n] r 0:0-1:1 10 0 this register holds the histogram measured value. there are 10 registers which keep the statistic value of a histogram measure for a particular lane until a new measure is launched. these values indicate the eye opening and jitter for each measured lane.the counter value is used to select the tap intable 88. table 87 spi-4 histogram counter register (blo ck base=0x0900 register offset=0x02-0x0b ) 118 of 162 october 20, 2006 idt idt88k8483 spi-4 bit alignment result register spi-4 egress data lane timing register spi-4 egress data control lane timing register field read / write bits length reset state description tap[7:0] r/w 0:0-0:7 8 0 tap[3:0] covers the range of taps from 0 to 8. tap[7:4] covers the range of taps from 5 to 14. the value selected from the counter register field c[n] table 87, is writ- ten into the tap field. this is used to select the received bit stream from the 10 samples after the histogram measure is launched.there are 19 registers in total. note: please refer to spi-4 ingress block diagram (p. 43) and spi-4 egress state block diagram (p. 46) for bit alignment overview . table 88 spi-4 bit alignment result register (blo ck base=0x0900 register offset=0x0c-0x1e ) field read / write bits length reset state description dtc0[1:0] r/w 0:0-0:1 2 0 this register is used to manually align the phase of data lane n by adding between 0.1 and 0.3 clock cycles of delay. dtcn [1:0] is used for adding 0.1 clock cycle units of output delay to the spi- 4 egress data lane n. dtcn[1:0]=0=no added delay. dtcn[1:0]=1=add 0.1 clock cycle of delay to data lane n. dtcn[1:0]=2=add 0.2 clock cycles of delay to data lane n. dtcn[1:0]=3=add 0.3 clock cycles of delay to data lane n. dtc1[1:0] r/w 0:2-0:3 2 0 .r/w20 dtc15[1:0] r/w 3:6-3:7 2 0 table 89 spi-4 egress data lane timing control (block base=0x0900, register offset=0x2a ) field read / write bits length reset state description ctltc[1:0] r/w 0:0-0:1 2 0 this register is used to manually align the phase of the control lane by adding between 0.1 clock cycle and 0.3 clock cycles of delay. ctltc [1:0] used for adding 0.1 clock cycle units of output delay to the spi-4 egress control output. ctltc [1:0]=0=no added delay. ctltc [1:0]=1=add 0.1 clock cycle of delay to the control output. ctltc [1:0]=2=add 0.2 clock cycles of delay to the control output. ctltc [1:0]=3=add 0.3 clock cycles of delay to the control output. table 90 spi-4 egress data control lane timing cont rol (block base=0x0900, register offset=0x2b ) 119 of 162 october 20, 2006 idt idt88k8483 spi-4 egress data clock timing register spi-4 egress status timing register field read / write bits length reset state description dctc[0:3] r/w 0:0-0:3 4 0 this register is used to manually align the phase of the spi-4 egress data clock to the data and control lanes by adding from 0.1 clock cycle to 0.9 clock cycles of delay to the data clock output. note that the clock delay value is not monotonically related to the value encoded in the bit field [3:0]. dctc [3:0] used for adding 0.1 clock cycle units of output delay to the spi-4 egress data clock. [3:0]=0=no added delay [3:0]=1=add 0.1 clock cycle of delay to the spi-4 egress data clock. [3:0]=3=add 0.2 clock cycles of delay to the spi-4 egress data clock. [3:0]=2=add 0.3 clock cycles of delay to the spi-4 egress data clock. [3:0]=7=add 0.4 clock cycles of delay to the spi-4 egress data clock. [3:0]=6=add 0.5 clock cycles of delay to the spi-4 egress data clock. [3:0]=4=add 0.6 clock cycles of delay to the spi-4 egress data clock. [3:0]=5=add 0.7 clock cycles of delay to the spi-4 egress data clock. [3:0]=f=add 0.8 clock cycles of delay to the spi-4 egress data clock. [3:0]=e=add 0.9 clock cycles of delay to the spi-4 egress data clock. table 91 spi-4 egress data clock timing contro l (blockbase=0x0900, register offset=0x2c ) field read / write bits length reset state description stc0[0:1] r/w 0:0-0:1 2 0 this register is used to manually align the phase of the status lane n by adding from 0.1 clock cycle to 0.3 clock cycles of delay. the stc0[1:0] and stc0[1:0] fields are valid only for lvds status and are not used for lvttl status. stcn [1:0] used for adding 0.1 clock cycle units of output delay to spi- 4 egress status lane n. [1:0]=0=no added delay. [1:0]=1=add 0.1 clock cycle of delay to status lane n. [1:0]=2=add 0.2 clock cycles of delay to status lane n. [1:0]=3=add 0.3 clock cycles of delay to status lane n. stc1[0:1] r/w 0:2-0:3 2 0 table 92 spi-4 egress status timing control (b lock base=0x0900, register offset=0x2d ) 120 of 162 october 20, 2006 idt idt88k8483 spi-4 egress status clock timing register packet fragment processor (pfp) registers pfp buffer segmen t assign table there are 64 registers in th is table, one for each lid. field read / write bits length reset state description sctc[0:3] r/w 0:0-0:3 4 0 this register is used to manually align the phase of the spi-4 egress status clock to the status outputs by adding from 0.1 clock cycle to 0.9 clock cycles of delay to the status clock output. note that the clock delay value is not monotonically related to the value encoded in the bit field [3:0]. the sctc[3:0] field is valid only for lvds status, not for lvttl status. sctc [3:0] used for adding 0.1 unit intervals of output delay to the spi- 4 egress status clock output. [3:0]=0=no added delay [3:0]=1=add 0.1 clock cycle of delay t o the spi-4 egress status clock [3:0]=3=add 0.2 clock cycles of delay to the spi-4 egress status clock [3:0]=2=add 0.3 clock cycles of delay to the spi-4 egress status clock [3:0]=7=add 0.4 clock cycles of delay to the spi-4 egress status clock [3:0]=6=add 0.5 clock cycles of delay to the spi-4 egress status clock [3:0]=4=add 0.6 clock cycles of delay to the spi-4 egress status clock [3:0]=5=add 0.7 clock cycles of delay to the spi-4 egress status clock [3:0]=f=add 0.8 clock cycles of delay to the spi-4 egress status clock [3:0]=e=add 0.9 clock cycles of delay to the spi-4 egress status clock table 93 spi-4 egress status clock timing control (block base=0x0900, register offset=0x2e ) field read / write bits length reset state description m r/w 0:0-1:0 9 0 maximum number of data buffer segments per lid of the available 508 segments in the pfp. reserved r 1:1-1:7 7 thr_starv r/w 2:0-2:7 8 0 indicates the starving threshold. status is set to starving if the number of free seg- ments in the data buffer is more than or equal to the starving threshold thr_hung r/w 3:0-3:7 8 0 indicates the hungry threshold. status is set to hungry if the number of free seg- ments in the data buffer is less than or equal to the starving thresholds but greater than or equal to the hungry threshold. status is set to satisfied if the number of free segments in the data buffer is greater than the hungry threshold. table 94 pfp buffer segment assign table (block base=0x01000/0x1800, regi ster offset=0x00-0x3f ) 121 of 162 october 20, 2006 idt idt88k8483 pfp packet length thresholds there are 64 registers in th is table, one for each lid. pfp queue diagnose table there are 64 registers in this table, one for each lp. pfp packet diagnose table there are 64 registers in th is table, one for each lid. field read / write bits length reset state description len_min r/w 0:0-0:7 8 0x40 used to configure the minimum packet length that the pfp is expected to receive. if the packet length is less than len_min, then the event is detected by the pfp and forwarded to pmon. the value in len_min does not affect the behavior of the data path and is only intended for diagnostics purposes. reserved r/w 1:0-1:7 8 0 len_max r/w 2:0-3:5 14 0x5ee used to configure the maximum packet length that the pfp is expected to receive. if the packet length is greater than len_max, then the event is detected by pfp and forwarded to pmon. the value in len_max does not affect the behavior of the data path and is only intended for diagnostics purposes. table 95 pfp packet length thresholds (block base=0x1100/0x1900, register offset=0x00-03f ) field read / write bits length reset state description unit r/w 0:0-1:1 10 0 the number of units waiting in the pfp queue for transfer to the egress interface. a unit corresponds to a packet or packet fragment , depending on the value of prt_mode in table 101 reserved r 1:2-2:3 10 0 read_pointer r/w 2:4-3:7 12 0 the value in this field indicates the circular queue read pointer position. table 96 pfp queue diagnose table (block ba se=0x1200/0x1a00, regist er offset=0x00-0x3f ) field read / write bits length reset state description pkt_num r/w 0:0-1:1 10 0 indicates the number of packets stored in the pfp segmented buffer. table 97 pfp packet diagnose table (block base= 0x1300/0x1b00, register offset=0x00-03f ) 122 of 162 october 20, 2006 idt idt88k8483 pfp egress burst size table there are 64 registers in th is table, one for each lid. pfp egress weight a nd direction register there are 64 registers in th is table, one for each lid. field read / write bits length reset state description max_burst_s r/w 0:0-0:3 4 0xf t he maximum data burst size transferred to the egress interface when a starving status signal is received. the actual burst size is equal to (max_burst_s+1)*16 bytes max_burst_h r/w 0:4-0:7 4 0xf t he maximum data burst size transferred to the egress interface when a hungry sta- tus signal is received. the actual burst size is equal to (max_burst_h+1)*16 bytes. note: the max_burst_h and max_burst_s values relate to maxburst2 and maxburst1 parameters in the oif spi-4 implementation agreement ( oif-spi-4- 02.1). table 98 pfp egress burst size table (block ba se=0x1400/0x1c00, register offset=0x00-0x3f ) field read / write bits length reset state description dir[1:0] r/w 0:0-0:1 2 11 indicates the pfp lid direction. each lid has 4 directions. t-m pfp m-t pfp ------------------------------------------------------------------------------ 00: main spi-4 tributary spi-4 01: redirect loopback 10: extract (obc for a) extract (obc for a) (prbs for b) (auxiliary for b) 11: discard discard weight r/w 0:2 1 0 this field sets the priority mode of the lids. this weight is used by the egress server scheduler to service the lids when the weight_en field in pfp queue weighting enable register (p. 124) is set to 1. 0: low priority for this lid, denoted by the register offset. 1:high priority for this lid, denoted by the register offset. note: please refer to page 52 for a detailed explanation of pfp weighing and scheduling. table 99 pfp egress weight and direction register (block base=0x1500/0x1d00, register offset=0x00-03f ) 123 of 162 october 20, 2006 idt idt88k8483 pfp egress packet mode control registers there are 64 registers, one for each lid. pfp link number configuration register pfp buffer management configuration register field read / write bits length reset state description pkt_mode r/w 0:0 1 0 this field is used to program the pfp egress to interleaved mode or packet mode. 0: interleaved mode. the lid is eligible to be served by the egress scheduler if there is one or more packet fragment in the queue.the transfer unit is one packet fragment. 1: packet mode. the lid is eligible to be served by the egress scheduler if there are one or more packets in the data memory.the transfer unit is one packet. ebp_en r/w 0:1 1 0 this control bit enables early backpressure propagation. 0: normal backpressure. 1:enable early backpressure propagation. table 100 pfp egress packet mode control register (b lock base=0x1600/0x1e00, register offset=0x00-0x3f ) field read / write bits length reset state description nr_lid r/w 0:0-0:2 3 0 link identifier (lid) number configuration. configures the maximum number of lids that the application will use for this pfp data buffer. once configured this value should not be changed without resetting the idt88k8483. nr_lid maximum number of lids 000 1 001 4 010 8 011 16 100 32 101 64 table 101 pfp link number configuration register (block base= 0x1700/0x1f00 , register offset=0x00 ) field read / write bits length reset state description buf_thr r/w 0:0-1:0 9 0x1c0 indicates the global threshold for segmented data buffer at which the backpressure is initiated. this field must be configured before the overbooking mode is enabled (ovbk_en = 1). unit is the number of lids. ovbk_en r/w 1:1 1 0 this indicates the manner in which the 508 data buffer segments in the pfp are managed. 0: non-overbooking mode.this means that the number of data buffer segments allo- cated to each lid is limited by the m field in pfp buffer segment assign table (p. 120) . 1:enable overbooking mode. this means that data buffer segments can now be shared between lids up to 8 times the value of m if free segments are available. table 102 pfp buffer management configuration register (block base=0x1700/0x1f00, register offset=0x01 ) 124 of 162 october 20, 2006 idt idt88k8483 pfp queue weighting enable register field read / write bits length reset state description weight_en r/w 0:0 1 0 this field selects which lid data needs to be transmitted first according to its priority set in the field weight in pfp egress weight and direction register (p. 122) , when non-satisfied status information is received in the fifo status channel. 0: the egress server scheduler schedules the lids in the calendar to be serviced in a two-priority round robin according to the starving, hungry and satisfied status of each lid. a starving status sets the lid priority high, a hungry status sets the prior- ity low. 1: the egress server schedules the lids with hungry or starving status to be ser- viced in a two-priority round robin scheme mode according to a fixed priority scheme. the status values of hungry and starving received in the egress status cal- endar are merged into a single non-satisfied status. the priority of the lid can be set in the weight field in the ?pfp egress weight and direction register? on page 122 . note: please refer to page 52 for a detailed explanation of pfp priority and scheduling. table 103 pfp queue weightin g enable register (block base= 0x1700/0x1f00 , register offset=0x02 ) 125 of 162 october 20, 2006 idt idt88k8483 pfp flow control register pfp test register field read / write bits length reset state description credit_en r/w 0:0 1 0 this field enables the information received over the fifo status channel to be interpreted as credit rather than status. 0:status mode. in status mode the spi-4 egress state used to schedule each lid remains the same until the received calendar status credit entry for the lid changes value. if the status is hungry or starving, transfers will continue until the status changes to satisfied even if fewer credits have been received than egress transfers. 1:credit enable. in this mode, the spi-4 egress will issue one credit?s worth data burst for the lid and then wait for another credit from the status channel before issuing another credit burst for that lid. burst_en r/w 0:1 1 0 this field enables bursts consisting of multiple transfers for the same lid to be made to the egress port buffers. this burst mode modifies the round-robin egress scheduler to prioritize those lids having multiple packet fragments or complete packets waiting for transfer. 0: burst not enabled. the spi-4 egress can transfer only one fragment of data for the scheduled lid to the egress port buffer. 1: burst enabled.the spi-4 egress can transfer more than one data segment to the egress port buffer. table 104 pfp flow control register (block base=0x1700/0x1f00, register offset=0x03 ) field read / write bits length reset state description repeat r/w 0:0 1 0 0: entries in the que ue, corresponding to pac kets or packet fragments stored in the data buffer are deleted once they are processed by the egress server. 1: entries in the queue are not deleted after they processed by the egress server. single_rep r/w 0:1 1 0 0: indicates that all 64 lids will be repeated. 1: indicates that only a single lid in field lid_repeat will be repeated. lid_repeat r/w 0:2-0:7 6 0 0: indicates the repeat operation is valid for all 64 lids. lid number: indicates the repeat operation is valid for a single lid. stop r/w 1:0 1 0 0: normal operation. 1: disables the service operation by stopping the egress server. single _stop r/w 1:1 1 0 0: stops service operation of all lids. 1: stops service operation of a single lid indicated by lid_stop. lid_stop r/w 1:2-1:7 6 0 0: indicates the stop operation is valid for all 64 lids. lid number: indicates the stop operation is valid for a single lid. table 105 pfp test register (block base= 0x1700/0x1f00 , register offset=0x04 ) 126 of 162 october 20, 2006 idt idt88k8483 pfp ingress status monitor register - 1 pfp ingress status monitor register - 2 pfp ingress status monitor register - 3 pfp ingress status monitor register - 4 field read / write bits length reset state description status[0] r 0:0-0:1 2 0 indicates status for lid 0 status[1:15] r 0:2-3:7 30 0 indicates status for lids 1-15 note: (1) the status has the same definition as described in the oif spi-4 implementation agreement (oif-spi-4-02.1) (2) the ingress status reflects the status based on the data buffer fill level. table 106 pfp ingress status monitor register - 1 (b lock base=0x1700/0x1f00, register offset=0x05 ) field read / write bits length reset state description status[16:31] r 0:0-3:7 32 0x00 indicates status for lid 16-31 table 107 pfp ingress status monitor register - 2 (b lock base=0x1700/0x1f00, register offset=0x06 ) field read / write bits length reset state description status[32:47] r 0:0-3:7 32 0x00 indicates status for lid 32-47 table 108 pfp ingress status mo nitor register - 3 (block base= 0x1700/0x1f00 , register offset=0x07 ) field read / write bits length reset state description status[48:63] r 0:0-3:7 32 0x00 indicates status for lid 48-63 table 109 pfp ingress status mo nitor register - 4 (block base= 0x1700/0x1f00 , register offset=0x08 ) [msb, lsb] status 10 satisfied 01 hungry 00 starving 11 reserved 127 of 162 october 20, 2006 idt idt88k8483 pfp egress status monitor register - 1 pfp egress status monitor register - 2 pfp egress status monitor register - 3 pfp egress status monitor register - 4 pfp internal parity e rror indication register field read / write bits length reset state description status[0:15] r 0:0-3:7 32 0x00 indicates status for lid 0-15 note: (1) the egress status has the same definition as described in the oif spi-4 implementation agreement (oif-spi-4-02.1) and is shown in pfp ingress sta- tus monitor register - 1 (p. 126) (2) the egress status reflects the status received from the status channel. table 110 pfp egress status monitor register - 1 (block base= 0x1700/0x1f00 , register offset=0x09 ) field read / write bits length reset state description status[16:31] r 0:0-3:7 32 0x00 indicates status for lid 16-31 table 111 pfp egress status monitor register - 2 (block base= 0x1700/0x1f00 , register offset=0x0a ) field read / write bits length reset state description status[32:47] r 0:0-3:7 32 0x00 indicates status for lid 32-47 table 112 pfp egress status monitor register - 3 (block base= 0x1700/0x1f00 , register offset=0x0b ) field read / write bits length reset state description status[48:63] r 0:0-3:7 32 0x00 indicates status for lid 48-63. table 113 pfp egress status monitor register - 4 (block base= 0x1700/0x1f00 , register offset=0x0c ) field read / write bits length reset state description p_error_i r/w 0:0 1 0 0: internal memory parity error did not occur. 1:internal memory pa rity error occurred. write 1: clear the field. p_error_ins r/wc 0:1 1 0 writing 1 generates a single parity error, self clear. table 114 pfp internal parity er ror indication register (block ba se=0x1700/0x1f00, register offset=0x0d ) 128 of 162 october 20, 2006 idt idt88k8483 pfp maximum packet length register field read / write bits length reset state description max_len r/w 0:0-0:5 6 6 this indicates the maximum packet length of the pfp. if maximum packet length is greater than or equal to max_len*256 by tes, the ingress server will truncate the packet, add sop/eop, add error tag accordingly and send cut-down event to pmon. the highest value that max_le n can be set to is 15, 872 bytes. table 115 pfp maximum packet length register (block base =0x1700/0x1f00, register offset=0x0e ) 129 of 162 october 20, 2006 idt idt88k8483 auxiliary registers auxiliary interface enable register auxiliary interface configuration register auxiliary extension buffer configuration register field read / write bits length reset state description aux_en r/w 0:0 1 0 this field enables the auxiliary interface 1 . 0:disable the auxiliary interface. 1:enable the auxiliary interface. aux_pdn r/w 0:1 1 0 this field powers down the auxiliary outputs except for the clock. 0:power up the auxiliary interface. 1:power down the auxiliary interface. note: 1 the interface has to be configured befor e enabling it.this is done in auxiliary in terface configuration register (p. 129) 2 the interface has to be powered down before configuring it to the qdr-ii interface mode or the generic interface mode table 116 auxiliary interface enable register (block base=0x0 a00, register offset=0x00 ) field read / write bits length reset state description mem r/w 0:0 1 0 this bit configures the auxiliary interface to qdr-ii mode or generic mode 1 . 0: generic interface mode. 1: qdr-ii interface mode. lidmdf r/w 0:1 1 0 this bit defines the manner in whic h the lid in the pfp is mapped to the fifos in the qdr-ii, for both status channel and data channel. 0: pfp lid x status channel is mapped to fifo x status channel in the external qdr-ii sram. fifo x data channel in the qdr-ii sram is mapped to the pfp lid x data channel. this setting is used when all pfp lid channels are mapped to qdr-ii fifos. 1: pfp lid x status channel is mapped to the (fifo x - lid_offset) status channel in the external qdr-ii sram. fifo x data ch annel in the qdr-ii sram is mapped to the pfp (lid x+ lid_offset) data channel. this setting is used when some lids are mapped to the qdr-ii fifos and other lids are mapped to the egress interface. note: 1 the interface has to be powered down before configuring it to the qdr ii interface mode or the generic interface mode table 117 auxiliary interface configuration register (block base= 0x0a00 , register offset=0x01 ) field read / write bits length reset state description ebc[2:0] r/w 0:2 3 0 determines the number of fifos that are configured in the external qdr-ii sram. please refer to table 119 for more information. table 118 auxiliary extension buffer conf iguration register (block ba se=0x0a00, register offset=0x02 ) 130 of 162 october 20, 2006 idt idt88k8483 auxiliary clock monitor status register ) external memory test control register ebc[2:0] number of fifo?s 3b?000 1 3b?001 4 3b?010 8 3b?011 16 3b?100 32 3b?101 64 3b?110 reserved 3b?111 reserved table 119 external memory segmentation field read / write bits length reset state description nclkav r 0:0 1 0 this field monitors the availability of the qdr-ii synchronous negative input clock, cqb. 0: clock not available. 1: clock available. pclkav r 0:1 1 0 this field monitors the availability of the qdr-ii synchronous positive input clock, cq. 0: clock not available. 1: clock available. note: refer to table 2 ?pin description? on page 28 for a brief description of the qdr-ii clocks. table 120 auxiliary clock monitor status register (block base= 0x0a00 , register offset=0x03 ) field read / write bits length reset state description test r/w 0:0 1 0 this field triggers the external qdr-ii sram test. 0: testing is not triggered. 1: testing is triggered. table 121 external memory test control register (block base=0x0a00, register offset=0x04 ) 131 of 162 october 20, 2006 idt idt88k8483 external memory test results register auxiliary early backpre ssure threshold register auxiliary packet mode configuration register hstl test register field read / write bits length reset state description test_done r 0:0 1 1 this field indicates the status of the external qdr-ii sram built-in self test. 0: test in progress. this bit is set to 0 when the test is triggered by writing 1 to the field test in table 121 . 1: test finished. error r 0:1 1 0 this field indicates the result of the external qdr-ii sram test. 0: no error. 1: some error with memory bist. table 122 external memory test results register (block base= 0x0a00 , register offset=0x05 ) field read / write bits length reset state description ebp_thr r/w 0:0-1:5 14 0x40 in the pfp to qdr-ii path, this field programs the threshol d in the qdr-ii fifo at which backpressure will be generated. if free space in the fifo is less than this threshold, backpressure is initiated towards the pfp egress by setting the fifo sta- tus to satisfied. this threshold is a global setting that is used by all fifos in the qdr-ii sram. table 123 auxiliary early backpres sure threshold register (block base= 0x0a00 , register offset=0x07 ) field read / write bits length reset state description pkt_mode r/w 0:0 1 0 this bit controls the mode of transfer from qdr-ii to pfp ingress. 0: cut through mode. in this mode, contiguous transfers from the qdr-ii sram to the pfp may contain interleaved packets. 1: packet mode.in this mode, whole packets are transferred from the qdr-ii sram to pfp. table 124 auxiliary packet mode configuration register (block base= 0x0a00 , register offset=0x08 ) field read / write bits length reset state description hstl_rx_test r/w 0:0 1 0 controls an internal test function in the hstl receiver. 0: normal operation 1: reserved for internal idt test table 125 auxiliary hstl receiver test control register (block base= 0x0a00 , register offset=0x0e ) 132 of 162 october 20, 2006 idt idt88k8483 auxiliary automatic impedance matching control register auxiliary synchronization status register field read / write bits length reset state description auto_measure r/w 0:0 1 0 writing 1 to this register will enable an automatic impedance measurement. set to 0 for normal operation. note: this register is used for diagnostic purpose only. table 126 auxiliary automatic impeda nce matching control register (blo ck base=0x0a00, re gister offset=0x0f ) field read / write bits length reset state description init_done r/w 0:0 1 0 this field indicates the initialization status. 0: auxiliary interface not initialized. 1: auxiliary interface initialized. alarm r/w 0:1 1 0 this field indicates the clock is not usable due to instability or excessive jitter. 0:no alarm, indicates that the clock is stable. 1:alarm due to an unstable clock or excessive jitter. table 127 auxiliary synchronizat ion status register (block ba se=0x0a00, regist er offset=0x12 ) 133 of 162 october 20, 2006 idt idt88k8483 auxiliary initialization control register prgd registers enable control register feedback configuration register bandwidth control registe r field read / write bits length reset state description init_trig r/w 0:0 1 0 write 1 to initialize synchronization of the auxiliary interface. auto_synch r/w 0:1 1 1 0:test mode, 1:embedded software controls initialization of the synchronization. table 128 auxiliary initialization control register (block base= 0x0a00 , register offset=0x013 ) field read/ write bits length reset state description gen r/w 0:0 1 0 this bit enables or disables the prbs generator. 0: disable prbs generator. 1: enable prbs generator. den r/w 0:1 1 0 this bit enables or disables the prbs detector. 0: disable prbs detector.the received prbs is not detected and the payload is discarded. 1: enables prbs detector to detect the received prbs. table 129 enable control register (block base= 0x0b00 , register offset=0x00 ) field read/ write bits length reset state description fbc r/w 0:0 - 0:7 8 0 this field defines the feedback function for generating the prbs sequence. fbc r/w 1:0 - 1:7 8 0xc0 this field defines the feedback function for generating the prbs sequence. fbc r/w 2:0 - 2:7 8 0 this field defines the feedback function for generating the prbs sequence. fbc r/w 3:0 - 3:7 8 0 this field defines the feedback function for generating the prbs sequence. table 130 feedback configuration register (b lock base=0x0b00, register offset =0x01) field read/ write bits length reset state description bw r/w 0:0 - 0:1 2 11 this field defines the bandwidth level for the prbs generator and checker as shown in table 126. table 131 bandwidth control register (b lock base=0x0b00, register offset=0x02) 134 of 162 october 20, 2006 idt idt88k8483 packet length register burst size register random control register bw bandwidth level 00 mclk 01 1/2 mclk 10 1/4 mclk 11 1/8 mclk table 132 bandwidth level as per field bw. field read/ write bits length reset state description p_len r/w 0:0 - 1:5 14 0xff this field determines the packet length to be generated using the prbs pattern. the actual packet length to be transmitted is p_len + 1. table 133 packet length register (block base=0x0b 00, register offset=0x03) field read/write bits length reset state description burst_s r/w 0:0 - 0:3 4 0xf this field determines the burst size of the packets gener- ated by the psbr packet ge nerator. the packets can be transmitted in a random or a fixed burst as determined by the burst_rand field in the random control register (p. 134) table 134 burst size register (block base=0x0b00, register offset=0x04) field read/write bits length reset state description plen_rand r/w 0:0 1 0 this bit determines if the packet length of the packets gen- erated by the psbr pac ket generator is random or fixed. 0: enable fixed packet length. it is fixed to p_len + 1. p_len is defined in packet length register (p. 134) . 1: enable random packet length. the packet length can be from 1 to p_len + 1. burst_rand r/w 0:1 1 0 this bit determines if the burst size of the packets to be transmitted is random or fixed. 0: enable fixed burst size. it is fixed to (burst_s+1)*16 bytes. burst_s is defined in burst size register (p. 134) . 1: enable random burst size. the burst size can vary from 16 bytes to (burst_s+1)*16 bytes. table 135 random control register (block base=0x0b00, register offset=0x05) 135 of 162 october 20, 2006 idt idt88k8483 lid register synchronization register bit error insertion registe r pmon registers field read/ write bits length reset state description lid r/w 0:0 - 0:5 6 0 this field indicates the lid which is selected to transfer the prbs packet burst. table 136 lid register (block base=0x0b00, register offset=0x06) field read/ write bits length reset state description syncv r/w 0:0 1 0 this field indicates the synchronization status of the prbs detector. 0: out of sync. 1: in sync. synci r/w 0:1 1 0 this field captures any transaction in the field syncv. 0: no change. 1: change in state from out of sync to in sync or vice-versa. write 1: clear note: (1)the out of sync status can be due to any one of 3 reasons. a) resetting the device. b) if field ?den? in enable control register (p. 133) is 0. c) if excessive errors between regenerated sequence from the received data and received sequence. (2) a transition from out of sync to in sync is caused by 48 consecutive error free bits. (3) in the in sync state, each mismatched bit will generate a bit error event and will be forwarded to pmon. table 137 synchronization register (b lock base=0x0b00, re gister offset=0x07) field read/ write bits length reset state description error_ins r/w 0:0 1 0 this field is used to insert a single bit error into the prbs generator. 0: bit error is not inserted. 1: 1 bit error is inserted after th e error is inserted, it auto clears. table 138 bit error insertion register (b lock base=0x0b00, re gister offset=0x08) 136 of 162 october 20, 2006 idt idt88k8483 pmon event interrupt indication register field read / write bits length reset state description t_inact_i r/w 0:0 1 0 tributary ingress inactive lp event. read 1: indicates occurrence of the event. read 0: indicates that the event has not occurred. write 1: clear the bit. m_inact_i r/w 0:1 1 0 main ingress inactive lp event. read 1: indicates occurrence of the event. read 0: indicates that the event has not occurred. write 1: clear the bit. tm_isop_i r/w 0:2 1 0 t-m illegal sop event. read 1: indicates occurrence of the event. read 0: indicates that the event has not occurred. write 1: clear the bit. tm_ieop_i r/w 0:3 1 0 t-m illegal eop event. read 1: indicates occurrence of the event. read 0: indicates that the event has not occurred. write 1: clear the bit. mt_isop_i r/w 0:4 1 0 m-t illegal sop event. read 1: indicates occurrence of the event. read 0: indicates that the event has not occurred. write 1: clear the bit. mt_ieop_i r/w 0:5 1 0 m-t illegal eop event. read 1: indicates occurrence of the event. read 0: indicates that the event has not occurred. write 1: clear the bit. tm_pktcd_i r/w 0:6 1 0 t-m packet cut down event. read 1: indicates occurrence of the event. read 0: indicates that the event has not occurred. write 1: clear the bit. mt_pktcd_i r/w 0:7 1 0 m-t packet cut down event. read 1: indicates occurrence of the event. read 0: indicates that the event has not occurred. write 1: clear the bit. t_lockun_i r/w 1:0 1 0 tributary spi4 ingress locker unavailable event. read 1: indicates occurrence of the event. read 0: indicates that the event has not occurred. write 1: clear the bit. m_lockun_i r/w 1:1 1 0 main spi4 ingress locker unavailable event. read 1: indicates occurrence of the event. read 0: indicates that the event has not occurred. write 1: clear the bit. t_dclklos_i r/w 1:2 1 0 tributary ingress data clock loss event. read 1: indicates occurrence of the event. read 0: indicates that the event has not occurred. write 1: clear the bit. table 139 pmon event interrupt indica tion register (block base =0x0f00, regist er offset=0x00 ) 137 of 162 october 20, 2006 idt idt88k8483 t_sclklos_i r/w 1:3 1 1 tributary egress status clock loss event. read 1: indicates that the event has not occurred. read 0: indicates occurrence of the event. write 1: clear the bit. m_dclklos_i r/w 1:4 1 0 main ingress data clock loss event. read 1: indicates occurrence of the event. read 0: indicates that the event has not occurred. write 1: clear the bit. m_sclklos_i r/w 1:5 1 0 main egress status clock loss event. read 1: indicates occurrence of the event. read 0: indicates that the event has not occurred. write 1: clear the bit. t_dip2_i r/w 1:6 1 0 tributary spi4 dip-2 event. read 1: indicates occurrence of the event. read 0: indicates that the event has not occurred. write 1: clear the bit. t_dip4_i r/w 1:7 1 0 tributary spi4 dip-4 event. read 1: indicates occurrence of the event. read 0: indicates that the event has not occurred. write 1: clear the bit. t_buserr_i r/w 2:0 1 0 tributary spi4 bus error event. read 1: indicates occurrence of the event. read 0: indicates that the event has not occurred. write 1: clear the bit. t_isync_i r/w 2:1 1 0 tributary ingress synch status change event. read 1: indicates occurrence of the event. read 0: indicates that the event has not occurred. write 1: clear the bit. t_esync_i r/w 2:2 1 0 tributary egress synch status change event. read 1: indicates occurrence of the event. read 0: indicates that the event has not occurred. write 1: clear the bit. m_dip2_i r/w 2:3 1 0 main spi4 dip-2 event. read 1: indicates occurrence of the event. read 0: indicates that the event has not occurred. write 1: clear the bit. m_dip4_i r/w 2:4 1 0 main spi4 dip-4 event. read 1: indicates occurrence of the event. read 0: indicates that the event has not occurred. write 1: clear the bit. field read / write bits length reset state description table 139 pmon event interrupt indica tion register (block base =0x0f00, regist er offset=0x00 ) 138 of 162 october 20, 2006 idt idt88k8483 m_buserr_i r/w 2:5 1 0 main spi4 bus error event. read 1: indicates occurrence of the event. read 0: indicates that the event has not occurred. write 1: clear the bit. m_isync_i r/w 2:6 1 0 main ingress synch status change event. read 1: indicates occurrence of the event. read 0: indicates that the event has not occurred. write 1: clear the bit. m_esync_i r/w 2:7 1 0 main egress synch status change event. read 1: indicates occurrence of the event. read 0: indicates that the event has not occurred. write 1: clear the bit. field read / write bits length reset state description table 139 pmon event interrupt indica tion register (block base =0x0f00, regist er offset=0x00 ) 139 of 162 october 20, 2006 idt idt88k8483 pmon event interrupt enable register field read / write bits length reset state description t_inact_en r/w 0:0 1 0 tributary ingress inactive lp. 0: disables the interrupt. 1: enables the interrupt. m_inact_en r/w 0:1 1 0 main ingress inactive lp. 0: disables the interrupt. 1: enables the interrupt. tm_isop_en r/w 0:2 1 0 t-m illegal sop. 0: disables the interrupt. 1: enables the interrupt. tm_ieop_en r/w 0:3 1 0 t-m illegal eop. 0: disables the interrupt. 1: enables the interrupt. mt_isop_en r/w 0:4 1 0 m-t illegal sop. 0: disables the interrupt. 1: enables the interrupt. mt_ieop_en r/w 0:5 1 0 m-t illegal eop. 0: disables the interrupt. 1: enables the interrupt. tm_pktcd_en r/w 0:6 1 0 t-m packet cut down. 0: disables the interrupt. 1: enables the interrupt. mt_pktcd_en r/w 0:7 1 0 m-t packet cut down. 0: disables the interrupt. 1: enables the interrupt. t_lockun_en r/w 1:0 1 0 tributary spi4 ingress locker unavailable. 0: disables the interrupt. 1: enables the interrupt. m_lockun_en r/w 1:1 1 0 main spi4 ingress locker unavailable. 0: disables the interrupt. 1: enables the interrupt. t_dclklos_en r/w 1:2 1 0 tributary ingress data clock lost. 0: disables the interrupt. 1: enables the interrupt. t_sclklos_en r/w 1:3 1 0 tributary egress status clock lost. 0: disables the interrupt. 1: enables the interrupt. m_dclklos_en r/w 1:4 1 0 main ingress data clock lost. 0: disables the interrupt. 1: enables the interrupt. m_sclklos_en r/w 1:5 1 0 main egress status clock lost. 0: disables the interrupt. 1: enables the interrupt. t_dip2_en r/w 1:6 1 0 tributary spi4 dip-2. 0: disables the interrupt. 1: enables the interrupt. table 140 pmon event interrupt enable register (block base= 0x0f00, register offset=0x01 ) 140 of 162 october 20, 2006 idt idt88k8483 pmon buffer t-m overflo w indication register there are 2 registers. t_dip4_en r/w 1:7 1 0 tributary spi4 dip-4. 0: disables the interrupt. 1: enables the interrupt. t_buserr_en r/w 2:0 1 0 tributary spi4 bus error. 0: disables the interrupt. 1: enables the interrupt. t_isync_en r/w 2:1 1 0 tributary ingress synch status change. 0: disables the interrupt. 1: enables the interrupt. t_esync_en r/w 2:2 1 0 tributary egress synch status change. 0: disables the interrupt. 1: enables the interrupt. m_dip2_en r/w 2:3 1 0 main spi4 dip-2. 0: disables the interrupt. 1: enables the interrupt. m_dip4_en r/w 2:4 1 0 main spi4 dip-4. 0: disables the interrupt. 1: enables the interrupt. m_buserr_en r/w 2:5 1 0 main spi4 bus error. 0: disables the interrupt. 1: enables the interrupt. m_isync_en r/w 2:6 1 0 main ingress synch status change. 0: disables the interrupt. 1: enables the interrupt. m_esync_en r/w 2:7 1 0 main egre ss synch st atus change. 0: disables the interrupt. 1: enables the interrupt. note: writing a 1 to any field in this register, causes an interrupt to be generated based on the occurrence of that particular even t indicated in the corresponding field in table 139 . the interrupt appears as an active low on the intb pin in the microprocessor interface. field read / write bits length reset state description ovferflow[31:0] r/w 0:0-3:7 32 0 this register indicates the overflow on a per lid basis from the tributary to main spi-4 interface. bit 0 of register with offset 0x02 indicates overflow for lid 0, bit 3 for lid 3, bit 0 of 2nd register with offset 0x03 indicates overflow for lid 32 and so on. read 1: indicates overflow for that lid. read 0: indicates no overflow for that lid. write 1: clears the bit. table 141 pmon buffer t-m overflow indica tion register (block base= 0x0f00, register offset=0x02-0x03 ) field read / write bits length reset state description table 140 pmon event interrupt enable register (block base= 0x0f00, register offset=0x01 ) 141 of 162 october 20, 2006 idt idt88k8483 pmon buffer m-t overflo w indication register there are 2 registers. pmon buffer t-m overflow in terrupt control register there are 2 registers. pmon buffer m-t overflow in terrupt control register there are 2 registers. field read / write bits length reset state description overflow[31:0] r/w 0:0-3:7 32 0 this register indicates the overflow on a per lid basis from the main to tributary spi-4 interface. bit 0 of register with offset 0x04 indicates overflow for lid 0, bit 3 for lid 3, bit 0 of 2nd register with offset 0x05 indicates overflow for lid 32 and so on. read 1: indicates overflow for that lid. read 0: indicates no overflow for that lid. write 1: clears the bit. table 142 pmon buffer m-t overflow indica tion register (block base= 0x0f00, register offset=0x04-0x05 ) field read / write bits length reset state description ovf_en[31:0] r/w 0:0-3:7 32 0 this register enables or disables the overflow indication for the lids which is indicated in registers in table 141 .bit 0 of register with offset 0x06 is for lid 0 and bit 0 of register with offset 0x07 is for lid 32 and so on. 0: disables overflow indication in pmon buffer t-m overflow indication register. 1: enables overflow indication in pmon buffer t-m overflow indication register. table 143 pmon buffer t-m overflow interr upt control register (block base=0x0f00, register offset=0x06-0x07 ) field read / write bits length reset state description ovf_en r/w 0:0-3:7 32 0 this register enables or disables the overflow indication for the lids which is indicated in registers in table 142 .bit 0 of register with offset 0x08 is for lid 0 and bit 0 of register with offset 0x09 is for lid 32 and so on. 0: disables overflow indication in pmon buffer m-t overflow indication register. 1: enables overflow indication in pmon buffer m-t overflow indication register. table 144 pmon buffer m-t overflow interr upt control register (block base=0x0f00, register offset=0x08-0x09 ) 142 of 162 october 20, 2006 idt idt88k8483 pmon buffer overflow source register pmon t-m inactive tran sfer lp field register pmon m-t inactive transfer lp field register pmon t-m illegal sop ev ent lid field register pmon t-m illegal eop event lid field register field read / write bits length reset state description tm_ovf r 0:0 1 0 this is a field associated critical event. when there is an overflow in the 64 t-m lids, this event is generated. it is the or result of 64 lids. mt_ovf r 0:1 1 0 this is a field associated critical event. when there is an overflow in the 64 t-m lids, this event is generated. it is the or result of 64 lids. table 145 pmon buffer overflow source register (block base=0x0f00, register offset=0x0a ) field read / write bits length reset state description lp r 0:0-0:7 8 0 in the t-m direction, when a control word carries an inactive lp information, then this event is generated and this register indicates the lp connected to the event . table 146 pmon t-m inactive tran sfer lp field register (block ba se=0x0f00, register offset=0x0b ) field read / write bits length reset state description lp r 0:0-0:7 8 0 in the m-t direction, when a control word carries an inactive lp information, then this event is generated and this register indicates the lp connected to the event. table 147 pmon m-t inactive transfer lp field register (block base =0x0f00, register offset=0x0c ) field read / write bits length reset state description lid r 0:0-0:5 6 0 this event is generated when consecutive sops are received at the tributary spi4 interface. the lid connected with the event is indicated in the register. table 148 pmon t-m illegal sop event field register (block base=0x0f00, register offset=0x0d ) field read / write bits length reset state description lid r 0:0-0:5 6 0 this event is generated when consecutive eops are received at the tributary spi4 interface. the lid connected with the event is indicated in the register table 149 pmon t-m illegal eop event field register (block base=0x0f00, register offset=0x0e ) 143 of 162 october 20, 2006 idt idt88k8483 pmon m-t illegal sop event lid field register pmon m-t illegal eop event lid field register pmon t-m packet cut-do wn lid field register pmon m-t packet cut-down lid field register field read / write bits length reset state description lid r 0:0-0:5 6 0 this event is generated when consecutive sops are received at the main spi4 interface. the lid connected with the event is indicated in the register. table 150 pmon m-t illegal sop event field register (block base=0x0f00, register offset=0x0f ) field read / write bits length reset state description lid r 0:0-0:5 6 0 this event is generated when consecutive eops are received at the main spi4 interface. the lid connected with the event is indicated in the register table 151 pmon m-t illegal eop event fi eld register (block base=0 x0f00, register offset=0x10 ) field read / write bits length reset state description lid r 0:0-0:5 6 0 when the packet arriving at the tributary spi-4 interface is larger than the storage capability of the lid, this event is raised and the lid associated with the event is indicated. table 152 pmon t-m packet cut-down lid field register (blo ck base=0x0f00, regi ster offset=0x11 ) field read / write bits length reset state description lid r 0:0-0:5 6 0 when the packet arriving at the main is larger than the storage capability of the lid, this event is raised and the lid associated with the event is indicated. table 153 pmon m-t packet cut-down lid field register (block base =0x0f00, regist er offset=0x12 ) 144 of 162 october 20, 2006 idt idt88k8483 pmon per lid counter table note: the counter tables are subject to accumulati on of data from a point in time to another. pmon per module/int erface counter table note: the counter tables are subject to accumulation of dat a from a point in time to another based on the timebase. for the measure points please refer to figure 33 pmon measure points p.67 length register offset measure point reset state description 24 0x 6n 3,4 0 tributary ingress good packet counter 24 0x 6n+1 3,4 0 tributary ingress abort packet counter 24 0x6n+2 13,14 0 main ingress good packet counter 24 0x6n+3 13,14 0 main ingress abort packet counter 24 0x6n+4 18,19 0 tributary egress packets counter 24 0x6n+5 8,9 0 main egress packets counter note: (1) in the register offset column ?n? refers to the lid number, with n between 0 and 63. the register address of the counter fo r a partic- ular lid is derived from the offset address using the equation shown in the register offset column and adding it to the block_b ase. (2) for the measure point, refer to figure 33 pmon measure points p.67 table 154 pmon per lid counter table (block base=0x0c00, register offset=0x00-0x17f ) subject to accumulation length register offset measure point reset state description 29 0x00 3,4 0 tributary spi-4 ingress byte 26 0x01 1,2 0 tributary spi-4 ingress transfer spi4+insert+loop 8 0x02 6,7 0 t-m too long packet 8 0x03 6,7 0 t-m too short packet 16 0x04 21,22 0 tributary spi-4 dip-2 error 16 0x05 1,2 0 tributary spi-4 dip-4 error individual for a/b 29 0x06 13,14 0 main spi-4 ingress byte module a 26 0x07 12 0 main spi-4 ingress transfer 8 0x08 16,17 0 m-t too long packet 8 0x09 16,17 0 m-t too short packet module a 16 0x0a 11 0 main spi-4 dip-2 error module a 16 0x0b 12 0 main spi-4 dip-4 error module b 30 0x0c 10 0 prbs bit error module b 24 0x0d 5 0 auxiliary ingress transfer counter module b 24 0x0e 20 0 auxiliary egress transfer counter module b 24 0x0f 15 0 prbs ingress transfer counter module b 24 0x10 10 0 prbs egress transfer counter table 155 pmon per module/interface counter table (block base=0x0e00 re gister offset=0x00-0x10 145 of 162 october 20, 2006 idt idt88k8483 miscellaneous registers pmon timebase control register pmon 1ms timer register gpio direction register there are 3 registers.register offset 0x10 is for gpio 0. register offset 0x11 is fo r gpio 1and register offset 0x12 is for gpi o 2. field read / write bits length reset state description internal r/w 0:0 1 0 selects between the internal and external time base.please refer to table 144. timer r/w 0:1 1 0 selects the internal timer/obc as the timebase timing source. please refer to table 144. manual r/wc 0:2 1 0 manual time base trigger, self clear. table 156 pmon timebase control register (block base=0x8b00, register offset=0x00 ) manual timer internal timebase trigger bit 2 bit 1 bit 0 source xx0 external. x 1 1 internal timer. x01 external obc. table 157 timebase source table. field read / write bits length reset state description period r/w 0:0-2:1 18 0x1e600 the timer register specifie s the number of mclk for generation of a 1ms time interval. table 158 pmon 1ms timer register (block base=0x8b00, register offset=0x01 ) field read / write bits length reset state description dir_out r/w 0:0 1 0 this field controls the direction of general purpose io pins. the direction can be input or output. 0: the gpio pins act as input/read pins. 1: the gpio pins act as output/write pins. table 159 gpio direction register ( block base=0x8b00, register offset=0x10-0x12 ) 146 of 162 october 20, 2006 idt idt88k8483 gpio level register there are 3 registers. gpio link table there are 3 registers. version number register software version register field read / write bits length reset state description level r/w 0:0 1 1 this field controls th e logical level on the gpio pins.it indicates a logical high or a logical low. 0: logical low. 1: logical high. table 160 gpio level register ( block base=0x8b00, register offset=0x13-0x15 ) field read / write bits length reset state description address r/w 0:0- 1:7 16 0 this field defines the address of the bit to be selected. bit r/w 2:0- 2:4 5 0 this field defines which bit is to be selected at the address defined in the field address. reflect_en r/w 2:5 1 0 if this field is enabled, then the level field in table 160 reflects the status of the bit which is selected from the indirect address space. 0: disable. 1: enable. table 161 gpio link table ( block base=0x8b00, register offset=0x16-0x18 ) field read / write bits length reset state description ver r 0:0-0:7 8 0x01 this field indicates the version of the chip. id r 1:0-1:7 8 0xff this field indicates the chip id. table 162 version number register ( block base=0x8b00, register offset=0x30 ) field read / write bits length reset state description sw_ver r 0:0-0:7 8 0x01 this field indicates the software version of the chip. table 163 version number register ( block base=0x8b00, register offset=0x32 ) 147 of 162 october 20, 2006 idt idt88k8483 electrical and thermal specification absolute maximum ratings recommended operating conditions parameter symbol conditions min 1 1. functional and tested operating conditions are given in table absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. stresses beyond those listed may affect device reli ability or cause permanen t damage to the device. max unit core digital supply voltage v ddc12 v ss =0, t j= 25 c-0.31.5v i/o digital supply voltage for lvds v ddl12 -0.3 1.5 v i/o digital supply voltage for hstl v ddh15 -0.3 2.1 v i/o digital supply voltage for lvds v ddl25 -0.3 3 v i/o digital supply voltage for hstl v ddh25 -0.3 3 v i/o digital supply voltage for lvttl v ddt33 -0.3 4.5 v analog supply voltage v dda25 -0.3 4.5 v i/o input voltage for lvttl vin -0.5 v ddt33 +0.5 v i/o input voltage for lvds vinl -0.5 v ddl25 +0.5 v i/o input voltage for hstl vinl -0.5 v ddh15 +0.5/ v ddh25 +0.5 v latch-up current io - 100 ma esd performance (hbm) - 2000 v lead temperature, br package t l -+250 c lead temperature, bl package t l +245 c ambient operating temperature t a (industrial) -40 +85 c ambient operating temperature t a (commercial) 0 +70 c storage temperature t s -65 +150 c table 164 absolute maximum ratings parameter symbol conditions min typ max unit core digital supply voltage v ddc12 v ss =0 1.08 1.2 1.32 v i/o digital supply voltage for lvds v ddl12 v ss =0 1.14 1.2 1.26 v i/o digital supply voltage for hstl v ddh15 v ss =0 1.4 1.5 1.6 v i/o digital supply voltage for lvds v ddl25 v ss =0 2.375 2.5 2625 v i/o digital supply voltage for hstl v ddh25 v ss =0 2.375 2.5 2.625 v i/o digital supply voltage for lvttl v ddt33 v ss =0 3.0 3.3 3.6 v analog supply voltage v dda25 av ss =0 2.25 2.5 2.75 v table 165 recommended operating conditions (part 1 of 2) 148 of 162 october 20, 2006 idt idt88k8483 thermal characteristics reference for termination v tt v ss =0 0.7 v ddh15 /2 0.8 v i/o reference for ldvs v spi4a/b/c_vref v ss =0 1.14 1.2 1.26 v i/o reference for hstl v qdr_imp /v g_imp v ss =0 0.68 v ddh15 /2 0.8 v parameter symbol conditions value 1 1. typical power dissipation for 3 spi4 (lvds) interfaces is 1.5w. typical power dissipation for 2 spi4 (lvds) interfaces is 1.1w. typical power dissipation for 1spi4 (lvds) interface is 0.7w. typical power dissipation for 1 memory (hstl) interface is 0.4w. typical power dissipation for 0 memory (hstl) interface is 0.08w. maximum power dissipation total p t ta=25 c, f mclk =200 mhz 4.4w maximum power dissipation of core p vddc12 ta=25 c, f mclk =200 mhz 2w maximum power dissipation of each lvds spi-4 interface i/o p vddl25 ta=25 c, f mclk =200 mhz 0.5w maximum power dissipation of hstl i/o (memory interface) p vddh15/vddh25 ta=25 c, f mclk =200 mhz 0.4w power dissipation of lvttl i/o p vddt33 ta=25 c, f mclk =200 mhz 0.33w maximum power dissipation of analog circuits p vdda25 ta=25 c, f mclk =200 mhz 0.5w thermal resistance (junction to case) 2 2. test conditions follows standard test methods and procedures for measuring thermal impedance, per eia/jedec51. test board: 4 la yers (2s/2p) - 101.6mmx114.6mmx1.6mm. jc 0.3 c/w thermal resistance (ambient) 3 ja air flow 0.0 m/s 12.6 c/w air flow 1.0 m/s 8.7 c/w air flow 2.0 m/s 7.2 c/w air flow 3.0 m/s 6.5 c/w air flow 4.0 m/s 6 c/w air flow 5.0 m/s 5.8 c/w thermal resistance (junction to board) 3 jb 2.85 c/w table 166 thermal characteristics parameter symbol conditions min typ max unit table 165 recommended operating conditions (part 2 of 2) 149 of 162 october 20, 2006 idt idt88k8483 dc characteristics parameter symbol conditions min typ max unit cmos i/o low-level input voltage v il --0.8v high-level input voltage v ih 2.0 - - v low-level output voltage v ol current=2ma - - 0.4 v high-level output voltage v o h current=2ma 2.4 - - v schmitt trigger input - low-level voltage v tl --1.19v schmitt trigger input - high-level voltage v th 1.5 - - v i/o off state leakage current i oz -10 0 +10 a pull-up resistor in input/bidirectional i/o rpu 60 90 130 ? pull-down resistor in input/bidirec- tional i/o rpd 50 85 160 ? lvttl i/o low-level input voltage v il --0.8v high-level input voltage v ih 2.0 - - v low-level output voltage v ol current=2ma - - 0.4 v high-level output voltage v o h current=2ma 2.4 - - v schmitt trigger input - low-level voltage v tl --1.19v schmitt trigger input - high-level voltage v th 1.5 - - v i/o off state leakage current i oz -10 0 +10 a pull-up resistor in input/bidirectional i/o rpu 60 90 130 ? pull-down resistor in input/bidirec- tional i/o rpd 50 85 160 ? lvds i/o input differential voltage v idth -100 - 100 mv input differential impedance r in 80 100 120 low-level output voltage v ol r term =100 0.925 - - v high-level output voltage v oh r term =100 - - 1.475 v output offset voltage v os 1125 - 1275 mv output differential voltage |v od |r term =100 250 325 400 mv output differential impedance r o 80 100 120 output short circuit current i os output shorted to gnd - - 24 ma table 167 dc characteristics (part 1 of 2) 150 of 162 october 20, 2006 idt idt88k8483 ac characteristics differential output short circuit cur- rent i osd +/- outputs shorted together - - 12 ma hstl i/o low-level input voltage v il -0.3 - v qdr_vre f -0.1 v high-level input voltage v ih v qdr_vre f +0.1 -v ddh25 + 0.3 v low-level output voltage v ol driver calibrated to 50 --0.4v high-level output voltage v o h driver calibrated to 50 v ddh25 - 0.4 --v parameter symbol conditions min typ max 1 unit clock interface. reference clock (spi4m_rclk, spi4b_rclk, spi4a_rclk) frequency div4=0 19.44 28.125 mhz reference clock duty cycle div4=0 30 50 70 % reference clock ppm div4=0 30 ppm reference clock frequency div4=1 77.76 112.5 mhz reference clock duty cycle div4=1 30 50 70 % reference clock ppm div4=1 30 ppm mclk internal clock frequency 124 200 mhz spi-4 interface lvds input. dclk clock frequency 77.76 450 mhz sclk clock frequency 77.76 450 mhz dclk clock duty cycle 45 50 55 % sclk clock duty cycle 45 50 55 % fall time (20%, 80%) tia/eia-644 300 500 ps rise time (20%, 80%) tia/eia-644 300 500 ps differential skew (p to n) t skew1 50 ps clock jitter tolerance 0.44 ui data skew tolerance 2ui input data jitter tolerance 0.13 ui spi-4 interface lvds output. figure tbd. dclk clock frequency 77.76 450 mhz sclk clock frequency 77.76 450 mhz table 168 ac characteristics (part 1 of 4) parameter symbol conditions min typ max unit table 167 dc characteristics (part 2 of 2) 151 of 162 october 20, 2006 idt idt88k8483 dclk clock duty cycle 45 50 55 % sclk clock duty cycle 45 50 55 % fall time (20%, 80%) i f all tia/eia-644 300 500 ps rise time (20%, 80%) i rise tia/eia-644 300 500 ps differential skew (p to n) t skew1 50 ps dclk and sclk peak to peak jitter 0.1 ui dat and ctl peak to peak jitter 0.24 ui clock-to-output propagation delay. this value is programmable. 2 0.6 ui spi-4 interface lvttl. sclk clock frequency 19.44 112.5 mhz sclk clock duty cycle 40 50 60 % input setup time 2ns input hold time 0.5 ns clock-to-output propagation delay: 1 1.2 ns auxiliary interface - qdr-ii / generic. figure 46 auxiliary interface - qdr- ii / generic - write access p.154 and figure 47 . auxiliary interface clock frequency faux 133 200 mhz auxiliary interface clock period (1/ f aux )t 7.51 5 ns auxiliary interface clock duty cycle 40 60 % clock to write valid tkwv 0.2t 0.3t ?t? is in ns clock to address valid tkav 0.2t 0.3t ?t? is in ns clock to data valid tkdv 0.2t 0.3t ?t? is in ns clock to read valid tkrv 0.2t 0.3t ?t? is in ns echo clock to data setup tqvd -0.4 ns echo clock to data hold tqhd -0.4 ns mcu interface - motorola mode - non mu ltiplexed bus (mpm=0). read cycle. figure 48 mcu interface - motorola mode - read access p.155 . read cycle time trc tdw+ tre- covery ns valid dsb+csb width tdw tprd ns delay from dsb to valid read signal trwv 2tmax-2 ns r/wb to dsb hold time trwh 4t ns delay from dsb to valid address tav 2tmax-2 ns address to dsb hold time tadh trwh ns dsb to valid read data propagation delay tprd 6t ns delay from read data active to high z tdaz 10 ns recovery time from read cycle trecovery 5 ns parameter symbol conditions min typ max 1 unit table 168 ac characteristics (part 2 of 4) 152 of 162 october 20, 2006 idt idt88k8483 mcu interface - motorola mode - non mu ltiplexed bus (mpm=0). write cycle. figure 49 mcu interface - motorola mode - write access p.155 . internal master clock (mclk) frequency (defined by the main clock generator) f 124 200 mhz write cycle time twc tdw+tre- covery ns valid dsb width tdw 6t ns delay from dsb to valid write signal trwv 2tmax-2 ns r/wb to dsb hold time trwh 6t ns delay from dsb to valid address tav 2tmax-2 ns address to dsb hold time tah 4t ns delay from dsb to valid write data tdv tav ns write data to dsb hold time tdhw tah ns recovery time from write cycle trecovery 5 ns mcu interface - intel mode - non mult iplexed bus (mpm=1). read cycle. figure 50 mcu interface - intel mode - read access p.156 . internal master clock (mclk) frequency (defined by main clock generator) f 124 200 mhz read cycle time trc trdw+ trecovery ns valid rdb width trdw tprd ns delay from rdb to valid address tav 2tmax-2 ns address to rdb hold time tah 4t ns rdb to valid read data propagation delay tprd 6tmax ns delay from read data active to high z tdaz 10 ns recovery time from read cycle trecovery 5 ns mcu interface - intel mode - non mult iplexed bus (mpm=1). write cycle. figure 51 mcu interface - intel mode - write access p.156 . internal master clock (mclk) period (defined by clock_generator) t 124 200 mhz write cycle time twc twrw+tr ecovery ns valid wrb width twrw 6t ns delay from wrb to valid address tav 2tmax-2 ns address to wrb hold time tah 4t ns delay from wrb to valid write data tdv tav ns write data to wrb hold time tdhw tah ns recovery time from write cycle trecovery 5 ns serial peripheral interface. figure 53 serial peripheral interface p.158 . parameter symbol conditions min typ max 1 unit table 168 ac characteristics (part 3 of 4) 153 of 162 october 20, 2006 idt idt88k8483 timing diagram sclk frequency fop 2.0 mhz min. /cs high time tcsh 100 ns /cs setup time tcss 50 ns /cs hold time tcsd 100 ns clock disable time tcld 50 ns clock high time tclh 205 ns clock low time tcll 205 ns data setup time tdis 50 ns data hold time tdih 150 ns output delay tpd 150 ns output disable time tdf 50 ns jtag interface. figure 54 jtag interface p.158 . tck frequency 10 mhz tck duty cycle 40 60 % tms setup tstms 20 ns tms hold thtms 20 ns tdi setup tsdti 20 ns tdi hold thdti 20 ns tck low to tdo valid tptdo 2 50 ns 1. tmax = 1000/fmin. 2. this value is programmable by tci[0:1] field in the spi-4 egress data lane timing register (p. 118) ctltc[0:1] field in the spi-4 egress data control lane timing register (p. 118) dctc[0:1] field in the spi-4 egress data clock timing register (p. 119) stci[0:1] field in the spi-4 egress status timing register (p. 119) sctc[0:3] field in the spi-4 egress status clock timing register (p. 120), parameter symbol conditions min typ max 1 unit table 168 ac characteristics (part 4 of 4) 154 of 162 october 20, 2006 idt idt88k8483 figure 46 auxiliary interface - qdr-ii / generic - write access figure 47 auxiliary interface - qdr-ii / generic - read access k /k /w a d d00 d01 a0 a1 d10 d11 tkwv tkav tkdv tkdv k /k /r a cq /cq q a q00 q01 tkav tqvd tqhd tkrv 155 of 162 october 20, 2006 idt idt88k8483 figure 48 mcu interface - motorola mode - read access figure 49 mcu interface - motorola mode - write access a[x:0] valid address dsb+csb r/wb read d[7:0] trwv valid data tdaz tadh trwh tprd trc tdw tav trecovery a[x:0] valid address dsb+csb r/wb write d[7:0] trwv tdhw tah trwh twc tdw tav valid data tdv trecovery 156 of 162 october 20, 2006 idt idt88k8483 figure 50 mcu interface - intel mode - read access figure 51 mcu interface - intel mode - write access a[x:0] valid address valid data tdaz tah tprd trdw tav note: wrb should be tied to high trecovery trc read[7:0] csb+_rdb a[x:0] valid address valid data tdhw tah tdv trdw tav note: rdb should be tied to high trecovery trc write[7:0] wrb+csb 157 of 162 october 20, 2006 idt idt88k8483 figure 52 88k8483 top view pinout 1234567891011121314151617181920212223242526 a vddt33 dat2 dat1 dat0 a_esclk _l_p a_esclk _l_n a_id_p[3] a_id_n[3] a_id_p[8] a_id_n[8] id[13]_p_ a id[13]_n_ a a_idclk _p a_idclk _n a_ed_p[5] a_ed_n[5 ] a_ed_p[1 0] a_ed_n[1 0] edclk_p _a edclk_n _a a_isclk_ l_p a_isclk_ l_n a_bias vddt33 a b vss vss dat3 adr5 wrb a_esta_ l_p[1] a_esta_ l_n[1] a_id_p[2] a_id_n[2] a_id_p[7] a_id_n[7] id[12]_p_ a id[12]_n_ a a_id_p[15 ] a_id_n[15 ] a_ed_p[4] a_ed_n[4 ] a_ed_p[9] a_ed_n[9 ] ed[15]_p_ a ed[15]_n_ a a_ista_l _p[1] a_ista_l _n[1] a_ref vss vddh15 b c dat6 dat5 dat4 adr3 rdb a_esta_ l_p[0] a_esta_ l_n[0] a_id_p[1] a_id_n[1] a_id_p[6] a_id_n[6] id[11]_p_ a id[11]_n_ a a_id_p[14 ] a_id_n[14 ] a_ed_p[3] a_ed_n[3 ] a_ed_p[8] a_ed_n[8 ] ed[14]_p_ a ed[14]_n_ a a_ista_l _p[0] a_ista_l _n[0] a_isclk_ t qdr_q0 qdr_q8 c d dat7 adr2 adr4 intb csb a_esclk _t a_esta_ t[1] a_id_p[0] a_id_n[0] a_id_p[5] a_id_n[5] id[10]_p_ a id[10]_n_ a a_ectl_ p a_ectl_ n a_ed_p[2] a_ed_n[2 ] a_ed_p[7] a_ed_n[7 ] ed[12]_p_ a ed[12]_n_ a a_ed_n[1 3] a_ista_t [0] a_ista_t [1] qdr_d0 qdr_d8 d e adr0 adr1 spien mpm vss vss a_esta_ t[0] a_ictl_p a_ictl_n a_id_p[4] a_id_n[4] id[9]_p_a id[9]_n_a a_ed_p[0] a_ed_n[0 ] a_ed_p[1] a_ed_n[1 ] a_ed_p[6] a_ed_n[6 ] ed[11]_p_ a ed[11]_n_ a a_ed_p[1 3] a_trclk qdr_q4 qdr_q6 qdr_q17 e f m_esclk _l_p m_esta_ l_p[1] m_esta_ l_p[0] m_esclk _t vss vss vss vddl25 vddl25 vdda25 vss vddl12 vddl12 vddl25 vss vss vdda25 vddl25 vss vss a_clk_s el qdr_q2 qdr_d2 qdr_d4 qdr_d6 qdr_d17 f g m_esclk _l_n m_esta_ l_n_m[1] m_esta_ l_n[0] m_esta_ t[1] m_esta_ t[0] vss vss vddl25 vddl25 vdda25 vss vddl12 vddl 12 vddl25 vss vss vdda25 vddl25 vddh25 vtt075 a_lvdst a qdr_q1 qdr_q3 qdr_q5 qdr_q7 qdr_q16 g h m_id_p[3] m_id_p[2] m_id_p[1] m_id_p[0] m_ictl_ p vss vddl25 vddl25 vddc12 vddc12 vddc12 vddc12 vddc12 vddc12 vddc12 vddc12 vddc12 vddc12 vddc12 vtt075 tms qdr_d1 qdr_ d3 qdr_d5 qdr_d7 qdr_d16 h j m_id_n[3] m_id_n[2] m_id_n[1] m_id_n[0] m_ictl_ n vss vss vss vddc12 vddc12 vddc12 vddc12 vddc12 vddc12 vddc12 vddc12 vddc12 vddc1 2 vddc12 vtt075 testse qdr_q9 qdr_q10 qdr_q11 qdr_q12 qdr_q15 j k m_id_p[8] m_id_p[7] m_id_p[6] m_id_p[5] m_id_p[4] vss vss vss vddc12 vddc12 vss vss vss vss vss vss vss vddc12 vddc12 vss qdr_r qdr_d9 qdr_d10 qdr_d11 qdr_d12 qdr_d15 k l m_id_n[8] m_id_n[7] m_id_n[6] m_id_n[5] m_id_n[4] vss vdda25 vdda25 vddc12 vddc12 vss vss vss vss vss vss vss vddc12 vddc12 vss qdr_w qdr_q13 qdr_q14 qdr_a0 qdr_nk qdr_pk l m m_id_p[1 3] m_id_p[1 2] m_id_p[1 1] m_id_p[1 0] m_id_p[9] tck vddl12 vddl12 vddc12 vddc12 vss vss vss vss vss vss v ss vddc12 vddc12 vddh15 qdr_a17 qdr_d13 qdr_d14 qdr_a1 vss vddh15 m n m_id_n[1 3] m_id_n[1 2] m_id_n[1 1] m_id_n[1 0] m_id_n[9] tdo vddl12 vddl12 vddc12 vddc12 vss vss vss vss vss vss vss vddc12 vddc12 vddh15 qdr_a16 qdr_a4 q dr_a3 qdr_a2 qdr_ncq qdr_pcq n p m_idclk _p m_id_p[1 5] m_id_p[1 4] m_ectl_ p m_ed_p[0 ] bond1 vddl25 vddl25 vddc12 vddc12 vss vss vss vss vss vss vss vddc1 2 vddc12 vss qdr_a15 qdr_a5 q dr_a6 qdr_a7 qdr_a8 qdr_a9 p r m_idclk _n m_id_n[1 5] m_id_n[1 4] m_ectl_ n m_ed_n[0 ] bond0 vss vss vddc12 vddc12 vss vss vss vss vss vss vss vddc12 vddc1 2 vtt075 qdr_a14 qdr_a12 qdr_a11 qdr_a10 qdr_d18 qdr_q18 r t m_ed_p[5 ] m_ed[4]_ p[4] m_ed_p[3 ] m_ed_p[2 ] m_ed_p[1 ] vss vss vss vddc12 vddc12 vss vss vss vss vss vss vss vddc12 vddc1 2 vtt075 qdr_a13 qdr_q26 qdr_q25 qdr_q23 qdr_q21 qdr_q19 t u m_ed_n[5 ] m_ed_n[4 ] m_ed_n[3 ] m_ed_n[2 ] m_ed_n[1 ] vss vdda25 vdda25 vddc12 vddc12 vss vss vss vss vss vss vss vddc12 vddc12 vtt075 vss qdr_d26 qdr_d25 qdr_d23 qdr_d21 qdr_d19 u v m_ed_p[1 0] m_ed_p[9 ] m_ed_p[8 ] m_ed_p[7 ] m_ed_p[6 ] vss vddl25 vddl25 vddc12 vddc12 vddc12 vddc12 vddc12 vddc12 vddc12 vddc12 vddc12 vddc12 vddc12 vddh15 trstb qdr_q35 qdr_q34 qdr_q24 qdr_q22 qdr_q2 0 v w m_ed_n[1 0] m_ed_n[9 ] m_ed_n[8 ] m_ed_n[7 ] m_ed_n[6 ] vss vddl25 vddl25 vddc12 vddc12 vddc12 vddc12 vddc12 vddc12 vddc12 vddc12 vddc12 vddc12 vddc12 vddh15 tdi qdr_d35 qdr_d34 qdr_d24 qdr_d22 qdr_d20 w y m_edcl k_p m_ed_p[1 5] m_ed_p[1 4] m_ed_p[1 2] m_ed_p[1 1] vss vss vddl25 vddl25 vdda25 vss vddl12 vddl 12 vddl25 vss vss vdda25 vddl25 vddh25 vddh15 b_lvdst a qdr_q33 qdr_q32 qdr_d31 qdr_d30 qdr_q28 y aa m_edcl k_n m_ed_n[1 5] m_ed_n[1 4] m_ed_n[1 2] m_ed_n[1 1] vss vss vddl25 vddl25 vdda25 vss vddl12 vddl 12 vddl25 vss vss vdda25 vddl25 vss vss b_clk_s el qdr_d33 qdr_d32 qdr_q31 qdr_q30 qdr_d28 aa ab m_isclk _l_p m_ista_l _p[1] m_ista_l _p[0] m_ed_n[1 3] m_ed_p[1 3] div4 b_esta_t [0] b_ictl_p b_ictl_n b_id_p[4] b_id_n[4] b_id_p[9] b_id_n[9] b_ed_p[0] b_ed_n[0] b_ed_p[1] b_ed_n[1] b_ed_p[6] b_ed_n[6] b_ed_p[1 1] b_ed_n[1 1] b_ed_p[1 3] b_trclk vss qdr_q29 qdr_q27 ab ac m_isclk _l_n m_ista_l _n[1] m_ista_l _n[0] m_ista_t [0] gpio2 b_esclk _t b_esta_t [1] b_id_p[0] b_id_n[0] b_id_p[5] b_id_n[5] b_id_p[10 ] b_id_n[10 ] b_ectl_ p b_ectl_ n b_ed_p[2] b_ed_n[2] b_ed_p[7] b_ed_n[7] b_ed_p[1 2] b_ed_n[1 2] b_ed_n[1 3] b_ista_t [0] b_ista_t [1] qdr_d29 qdr_d27 ac ad m_bias m_ref m_isclk _t m_ista_t [1] gpio1 b_esta_l _p[0] b_esta_l _n[0] b_id_p[1] b_id_n[1] b_id_p[6] b_id_n[6] b_id_p[11 ] b_id_n[11 ] b_id_p[14 ] b_id_n[14 ] b_ed_p[3] b_ed_n[3] b_ed_p[8] b_ed_n[8] b_ed_p[1 4] b_ed_n[1 4] b_ista_l _p[0] b_ista_l _n[0] b_isclk_ t qdr_imp qdr_ref ad ae vss vss m_clk_s el timebas egpio0 b_esta_l _p[1] b_esta_l _n[1] b_id_p[2] b_id_n[2] b_id_p[7] b_id_n[7] b_id_p[12 ] b_id_n[12 ] b_id_p[15 ] b_id_n[15 ] b_ed_p[4] b_ed_n[4] b_ed_p[9] b_ed_n[9] b_ed_p[1 5] b_ed_n[1 5] b_ista_l _p[1] b_ista_l _n[1] b_ref vss vddh15 ae af vddt33 mrclk resetb m_lvdst a b_esclk _l_p b_esclk _l_n b_id_p[3] b_id_n[3] b_id_p[8] b_id_n[8] b_id_p[13 ] b_id_n[13 ] b_idclk_ p b_idclk_ n b_ed_p[5] b_ed_n[5] b_ed_p[1 0] b_ed_n[1 0] b_edclk _p b_edclk _n b_isclk_ l_p b_isclk_ l_n b_bias vddt33 af 1234567891011121314151617181920212223242526 158 of 162 october 20, 2006 idt idt88k8483 figure 53 serial peripheral interface figure 54 jtag interface /cs sclk sdi sdo tcsh tcss high impedance tcsd tclh tcll tdis tdih t pd tdf valid input valid output tcld high impedance tck tstdi tstms t pdo tdi tms tdo t htdi t htms 159 of 162 october 20, 2006 idt idt88k8483 mechanical data figure 55 br 672 fcbg package outline, rohs compliant 160 of 162 october 20, 2006 idt idt88k8483 document revision history the document revision history is described in table 169. issue date description 1.0 10/20/2006 general release table 169 document revision history 161 of 162 october 20, 2006 idt idt88k8483 corporate headquarters 6024 silver creek valley road san jose, ca 95138 for sales: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for tech support: email: spi@idt.com phone: 408-360-1716 ordering information the ordering information is described in table 170 . device code product IDT88K8483BRI idt88k8483 spi-4 exchange, industrial temperature, rohs 6 idt88k8483bli idt88k8484 spi-4 exchange, industrial temperature, rohs 5 table 170 ordering information 162 of 162 october 20, 2006 idt idt88k8483 |
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